Sense operation flags in a memory device

Patent metadata

Field	Value
Publication number	US-10126967-B2
Application number	US-201615342287-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Nov 9, 2010
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

First claim

What is claimed is:

1. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array;
programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed; and
loading user data into a dynamic data cache coupled to the first data lines prior to programming the memory cells coupled to the first data lines;
wherein programming the memory cells coupled to the first data lines in the main memory array comprises programming the memory cells coupled to the first data lines in the main memory array with the user data loaded into the dynamic data cache; and
wherein the flag memory array is a first flag memory array, and further comprising programming memory cells coupled to data lines in a second flag memory array with other flag data while programming the memory cells coupled to the first data lines.

2. The method of claim 1 , further comprising loading the other flag data into a portion of the dynamic data cache coupled to the data lines in the second flag memory array while loading the user data into the dynamic data cache.

3. The method of claim 1 , wherein programming the memory cells coupled to the data lines in the flag memory array comprises programming data that includes both the flag data and other data associated with a particular page of data of the main memory array.

4. The method of claim 1 , wherein the flag data comprises a plurality of bytes of data.

5. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array; and
programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed;
wherein the flag data comprises a plurality of bytes of data; and
wherein the plurality of bytes of data comprises a bit indicative of the memory cells coupled to the second data lines being programmed and bytes providing additional information about the memory cells coupled to the second data lines.

6. The method of claim 5 , wherein a first data line of the first data lines in the main memory array and a second data line of the second data lines in the main memory array are adjacent first and second data lines.

7. The method of claim 6 , wherein a read gate voltage of the memory cell coupled to the first data line of the adjacent first and second data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed.

8. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array; and
programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed;
wherein a first data line of the first data lines in the main memory array and a second data line of the second data lines in the main memory array are adjacent first and second data lines; and
wherein the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed is to be read concurrently with the memory cell coupled to the first data line of the adjacent first and second data lines.

9. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array;
programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to first data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed; and
inhibiting memory cells coupled to third data lines in the main memory array while programming memory cells coupled to third data lines in the flag memory array with flag data indicative of the memory cells coupled to the third data lines not being programmed;
wherein a third data line of the third data lines in the main memory array and a first data line of the first data lines in the main memory array are adjacent first and third data lines; and
wherein the flag data indicative of the memory cell coupled to the third data line of the adjacent first and third data lines not being programmed is to be read concurrently with the memory cell coupled to the first data line of the adjacent first and third data lines.

10. The method of claim 9 , wherein a read gate voltage of the memory cell coupled to the first data line of the adjacent first and third data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the third data line of the adjacent first and third data lines not being programmed.

11. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array;
programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to first data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed; and
inhibiting memory cells coupled to third data lines in the main memory array while programming memory cells coupled to third data lines in the flag memory array with flag data indicative of the memory cells coupled to the third data lines not being programmed;
wherein a first first data line of the first data lines in the main memory array and a third data line of the third data lines in the main memory array are adjacent first first and third data lines;
wherein a second first data line of the first data lines in the main memory array and a second data line of the second data lines in the main memory array are adjacent second first and second data lines; and
wherein a read gate voltage of the memory cell coupled to the first first data line of the adjacent first first and third data lines is to be adjusted, in response to the flag data indicative of the memory cell coupled to the third data line of the adjacent first first and third data lines not being programmed, differently than a read gate voltage of the memory cell coupled to the second first data line of the adjacent second first and second data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the second data line of the adjacent second first and second data lines being programmed.

12. A method for programming sense flags, the method comprising:
programming memory cells coupled to first data lines in a main memory array with first user data while programming memory cells coupled to first data lines in a first flag memory array with first flag data; and
programming memory cells coupled to second data lines in the main memory array with second user data while programming memory cells coupled to second data lines in the first flag memory array with second flag data and while programming memory cells coupled to data lines in a second flag memory array with third flag data indicative of the memory cells coupled to the second data lines being programmed.

13. The method of claim 12 , wherein the data lines in the second flag memory array are first data lines in the

Assignees

• Micron Technology Inc

Inventors

• Ahmed Shafqat
• Hasnat Khaled
• Kalavade Pranav
• Parat Krishna
• Yip Aaron
• Helm Mark A
• Bicksler Andrew

Classifications

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title