Hybrid control technique for power converters

Patent metadata

Field	Value
Publication number	US-10122286-B2
Application number	US-201815867212-A
Country	US
Kind code	B2
Filing date	Jan 10, 2018
Priority date	May 6, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A power conversion circuit includes a high-side MOSFET and a low-side MOSFET. A conduction terminal of the high-side MOSFET is coupled to a conduction terminal of the low-side MOSFET at a half-bridge (HB) circuit node. The high-side MOSFET is switched off. Voltage potential transitions of the HB circuit node are counted while the high-side MOSFET and low-side MOSFET are off. Assertion of a control signal to the low-side MOSFET is postponed for two voltage potential transitions of the HB circuit node after the high-side MOSFET is switched off. The low-side MOSFET is switched off by de-asserting the control signal to the low-side MOSFET. Switching on the high-side MOSFET is postponed for two voltage potential transitions of the HB circuit node after switching off the low-side MOSFET.

First claim

What is claimed:

1. A power conversion circuit, comprising:
a first transistor;
a second transistor including a conduction terminal coupled to a conduction terminal of the first transistor at a first node; and
a controller including a first output coupled to a control terminal of the first transistor and a second output coupled to a control terminal of the second transistor, wherein the controller monitors a voltage at the first node to delay turning on the first transistor until detecting a first peak of the voltage and further to delay turning on the second transistor until detecting a first valley of the voltage after the first peak.

2. The power conversion circuit of claim 1 , wherein the controller monitors the voltage at the first node to delay turning on the first transistor until detecting a second peak of the voltage after the first valley and further to delay turning on the second transistor until detecting a second valley of the voltage after the second peak.

3. The power conversion circuit of claim 1 , wherein the controller includes:
a voltage sensor having an input coupled to the first node; and
a peak/valley detection circuit having an input coupled to an output of the voltage sensor and an output coupled to the control terminal of the first transistor and the control terminal of the second transistor.

4. The power conversion circuit of claim 3 , wherein the controller further includes:
a modulation circuit having an input coupled to the output of the peak/valley detection circuit; and
a driver circuit having an input coupled to an output of the modulation circuit and an output coupled to the control terminal of the first transistor and the control terminal of the second transistor.

5. The power conversion circuit of claim 3 , wherein the peak/valley detection circuit includes a counter configured to count peaks and valleys of the voltage at the first node.

6. The power conversion circuit of claim 1 , further including a switched capacitor coupled to the first node.

7. A controller for a power conversion circuit, comprising:
a first control output;
a second control output; and
a half-bridge input, wherein the controller is configured to monitor a voltage at the half-bridge input and alternatively delay assertion of the first control output for a first number of peaks of the voltage and delay assertion of the second control output for a second number of valleys of the voltage.

8. The controller of claim 7 , further including:
a voltage sensor having an input coupled to the half-bridge input; and
a peak/valley detection circuit having an input coupled to an output of the voltage sensor.

9. The controller of claim 8 , further including:
a modulation circuit having an input coupled to the output of the peak/valley detection circuit; and
a driver circuit having an input coupled to an output of the modulation circuit, wherein the driver circuit generates the first control output and second control output.

10. The controller of claim 8 , wherein the peak/valley detection circuit includes a counter configured to count peaks and valleys of the voltage at the half-bridge input.

11. The controller of claim 7 , further including a switched capacitor coupled to the half-bridge input.

12. The controller of claim 9 , wherein the driver circuit includes an LLC resonant mode half-bridge driver.

13. The controller of claim 7 , wherein the first number is equal to the second number.

14. A method for generating a voltage signal, comprising:
monitoring a signal on a half-bridge node to detect valleys and peaks of the signal;
asserting a high-side control signal during a first peak of the signal after skipping a first number of the peaks; and
asserting a low-side control signal during a first valley of the signal after skipping a second number of the valleys.

15. The method of claim 14 , wherein the first number is equal to the second number.

16. The method of claim 14 , further including:
counting the first number of the peaks during a first time period; and
counting the second number of the valleys during a second time period, wherein the first time period and second time period are non-overlapping.

17. The method of claim 14 , further including detecting valleys and peaks of the signal by monitoring a rate of change of a voltage potential of the signal.

18. The method of claim 14 , further including calculating the first number and second number based on a feedback signal.

19. The method of claim 14 , further including coupling a capacitance to the half-bridge node while skipping the first number of the peaks and the second number of the valleys.

20. The method of claim 19 , further including disconnecting the capacitance from the half-bridge node.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Stuler Roman

Classifications

• H02M2001/0058

  Electricity · mapped topic

• H02M2001/0009

  Electricity · mapped topic

• H02M3/33553 Primary

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/3376 Primary

  with automatic control of output voltage or current · CPC title