Current sense detection for synchronous rectification

Patent metadata

Field	Value
Publication number	US-10063154-B2
Application number	US-201615143239-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	Apr 29, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A power conversion circuit including an SR MOSFET is provided. A minimum off-time timer for the SR MOSFET is started. A voltage potential at a first terminal of the SR MOSFET is measured. The SR MOSFET is turned on after a rate of change over time of the voltage potential exceeds a first threshold and before the minimum off-time timer expires.

First claim

What is claimed:

1. A method of generating a voltage signal using a controller, comprising:
comparing a voltage potential at a current sense input of the controller against a first threshold;
comparing the voltage potential against a second threshold;
measuring a first amount of time between the voltage potential crossing the first threshold and the voltage potential crossing the second threshold; and
asserting a synchronous rectification (SR) control output of the controller after at least one of either a minimum off-time of the SR control output is exceeded or the first amount of time is measured below a third threshold.

2. The method of claim 1 , further including:
measuring an off-time of the SR control output using a minimum off-time timer; and
resetting the minimum off-time timer when the voltage potential is below a reset threshold.

3. The method of claim 1 , wherein measuring the first amount of time below the third threshold allows the SR control output to be asserted before the minimum off-time is exceeded.

4. The method of claim 1 , further including measuring the first amount of time using a timer circuit of the controller.

5. The method of claim 1 , further including asserting the SR control output when the voltage potential is below a turn-on threshold.

6. The method of claim 1 , further including deasserting the SR control output when the voltage potential is above a turn-off threshold.

7. A method of generating a voltage signal, comprising:
starting a minimum off-time timer;
measuring a voltage potential of a current sense input; and
asserting a synchronous rectification (SR) control output after a rate of change over time of the voltage potential exceeds a first threshold.

8. The method of claim 7 , further including asserting the SR control output before the minimum off-time timer expires.

9. The method of claim 7 , further including asserting the SR control output when the voltage potential falls below a second threshold.

10. The method of claim 7 , further including resetting the minimum off-time timer when the voltage potential falls below a second threshold.

11. The method of claim 7 , further including deasserting the SR control output after a minimum on-time is exceeded.

12. The method of claim 7 , further including measuring the rate of change over time of the voltage potential by:
starting a timer when the voltage potential crosses a second threshold; and
determining a value of the timer when the voltage potential crosses a third threshold.

13. The method of claim 12 , further including comparing the value of the timer against the first threshold.

14. A power conversion circuit controller, comprising:
a current sense input;
a first comparator including a first input coupled to the current sense input and a second input of the first comparator coupled to a first reference voltage potential;
a second comparator including a first input coupled to the current sense input and a second input of the second comparator coupled to a second reference voltage potential; and
a timer coupled to an output of the first comparator and an output of the second comparator and configured to measure an amount of time between assertion of the output of the first comparator and assertion of the output of the second comparator.

15. The power conversion circuit controller of claim 14 , further including a logic block comprising a first input of the logic block coupled to an output of the timer and an output terminal of the logic block coupled to a synchronous rectification (SR) control output.

16. The power conversion circuit controller of claim 15 , further including a minimum off-time timer coupled to the logic block.

17. The power conversion circuit controller of claim 16 , wherein the logic block is configured to assert a signal to the SR control output terminal after at least one of either the output of the timer is asserted or the minimum off-time timer expires.

18. The power conversion circuit controller of claim 14 , wherein the timer is configured to be started by the first comparator.

19. The power conversion circuit controller of claim 18 , wherein the timer is configured to assert an output of the timer if a transition of the output of the second comparator is detected with a value of the timer under a threshold value.

20. The power conversion circuit controller of claim 14 , wherein the second reference voltage potential is a lower voltage potential than the first reference voltage potential.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Ptacek Karel
• Tichy Tomas

Classifications

• H02M2001/0009

  Electricity · mapped topic

• H02M3/33523 Primary

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title