Inverter apparatus

Patent metadata

Field	Value
Publication number	US-2018115243-A1
Application number	US-201615335339-A
Country	US
Kind code	A1
Filing date	Oct 26, 2016
Priority date	Oct 26, 2016
Publication date	Apr 26, 2018
Grant date	—

Abstract

An inverter apparatus is provided for converting direct current to alternating current. The inverter apparatus includes a boost converter coupled between a power source and a bypass circuit, and a power inverter coupled between the bypass circuit and a load to generate an output voltage. The output voltage is powered by the power source directly via the bypass circuit without activating the boost converter when the output voltage is smaller than a threshold voltage. The output voltage is powered by the power source boosted by the boost converter when the output voltage is larger than the threshold voltage. High efficiency is achieved by bypassed the boost converter.

First claim

1 . An apparatus for converting a direct current to an alternating current, comprising:
a boost converter coupled between a power source and a bypass circuit, and a power inverter coupled between the bypass circuit and a load to generate an output voltage, wherein two switches of the power inverter are connected in series with two switches of the bypass circuit, wherein the output voltage is powered by the power source directly via the bypass circuit without activating the boost converter when the output voltage is smaller than a threshold voltage, and wherein the output voltage is powered by the power source boosted by the boost converter when the output voltage is larger than the threshold voltage.

2 . The apparatus of claim 1 , wherein when a half of an input source voltage of the power source is larger than the output voltage, a switch of the bypass circuit is performing pulse-width modulation (PWM), and another switch of the bypass circuit is turned off.

3 . The apparatus of claim 1 , wherein when a half of an input source voltage of the power source is larger than the output voltage, the two switches of the power inverter are turned off.

4 . The apparatus of claim 1 , wherein when a half of an input source voltage of the power source is less than the output voltage, a switch of the bypass circuit is turned on, and another switch of the bypass circuit is turned off.

5 . The apparatus of claim 1 , wherein the power inverter comprises four switches, a first switch of the power inverter is connected in series with a second switch of the power inverter, the first switch and the second switch of the power inventor are connected in parallel with a first switch of the bypass circuit, and wherein a third switch of the power inverter is connected in series with a fourth switch of the power inverter, the third switch and the fourth switch of the power inventor are connected in parallel with a second switch of the bypass circuit.

6 . The apparatus of claim 5 , wherein when a half of an input source voltage is less than the output voltage, the four switches of the power inverter are turned off, the first switch of the bypass circuit is turned on, and the second switch of the bypass circuit is turned off.

7 . The apparatus of claim 5 , wherein when a half of an input source voltage is less than the output voltage, the first switch and the fourth switch of the power inverter are turned on, the second switch of the power inverter is performing PWM, the third switch of the power inverter is turned off, and wherein the first switch of the bypass circuit is turned on, the second switch of the bypass circuit is turned off.

8 . The apparatus of claim 5 , wherein when a half of an input source voltage is larger than the output voltage, the first switch and the fourth switch of the power inverter are turned on, the second switch of the power inverter and the first switch of the bypass circuit are performing PWM, and wherein the third switch of the power inverter and the second switch of the bypass circuit are turned off.

9 . (canceled)

10 . The apparatus of claim 1 , wherein when a half of an input source voltage of the power source is larger than the output voltage, the two switches of the power inverter are turned off, and wherein a switch of the bypass circuit is performing PWM, and another switch of the bypass circuit is turned off.

11 . The apparatus of claim 1 , wherein when a half of an input source voltage of the power source is less than the output voltage, a switch of the power inverter is performing PWM, another switch of the power inverter is turned off, a switch of the bypass circuit is turned on, and another switch of bypass circuit is turned off.

12 . The apparatus of claim 1 , wherein the boost converter comprises a first converter and a second converter, each of the first converter and the second converter comprises two switches, and a circuit structure of the first converter is similar to that of the second converter.

13 . The apparatus of claim 1 , wherein the apparatus exhibits 7-level output.

14 . The apparatus of claim 1 , wherein the bypass circuit is located inside the power inverter.

15 . The apparatus of claim 1 , wherein the bypass circuit is located outside of the power inverter.

16 . A method for operating an inverter apparatus, wherein the apparatus comprises a boost converter coupled between a power source and a bypass circuit, and a power inverter coupled between the bypass circuit and a load, the boost converter comprising two switches, wherein two switches of the power inverter are connected in series with two switches of the bypass circuit, wherein the method comprises;
controlling the boost converter and the bypass circuit to power an output voltage directly from the power source via the bypass circuit without activating the boost converter when the output voltage is less than a voltage threshold, and wherein the two switches of the boost converter are switched off to deactivate the boost converter.

17 . The method of claim 16 , a switch of the bypass circuit is performing pulse-width modulation (PWM), and another switch of the bypass circuit is switched off.

18 . The method of claim 16 , wherein the method further comprises:
switching off the two switches of the power inverter when a half of an input source voltage of the power source is larger than the output voltage.

19 . The method of claim 16 , wherein the power inverter comprises four switches, a first switch of the power inverter is connected in series with a second switch of the power inverter, the first switch and the second switch of the power inventor are connected in parallel with a first switch of the bypass circuit, and wherein a third switch of the power inverter is connected in series with a fourth switch of the power inverter, the third switch and the fourth switch of the power inventor are connected in parallel with a second switch of the bypass circuit, wherein the method further comprises:
switching on the first switch and the fourth switch of the power controlling the second switch of the power inverter to perform PWM, and switching off the third switch of the power inverter.

20 . The method of claim 16 , wherein the method comprises:
generating 7 voltage levels for the output voltage.

21 . The method of claim 16 , wherein the method further comprises:
switching on a switch of the bypass circuit, and switching off another switch of the bypass circuit when a half of an input source voltage of the power source is less than the output voltage.

Assignees

• Futurewei Technologies Inc

Inventors

• Fu Dianbo

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M7/487

  Neutral point clamped inverters · CPC title

• H02J2101/24

  Photovoltaics · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title