Semiconductor device including stacked structure

Patent metadata

Field	Value
Publication number	US-10121798-B2
Application number	US-201715440647-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Sep 9, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a stacked structure on the substrate,
the stacked structure including units stacked on top of each other in a direction perpendicular to a top surface of the substrate,
the stacked structure including a hole passing through the stacked structure,
the units including first units and second units between the first units,
the first units includes a plurality of first gates and a plurality of first interlayer insulating layers alternately stacked on top of each other,
the second units including a plurality of a second gates and a plurality of second interlayer insulating layers alternately stacked on top of each other, on and
a ratio of a thickness of one of the plurality of second interlayer insulating layers with respect to a thickness of one of the plurality of second gates is different from a ratio of a thickness of one of the plurality of first interlayer insulating layers with respect to a thickness of one of the plurality of first gates; and

a vertical structure in the hole.

2. The semiconductor device of claim 1 , wherein
the hole includes first hole regions and a second hole region between the first hole regions, and
a width of the second hole region is greater than a width of the first hole regions adjacent to the second hole region.

3. The semiconductor device of claim 2 , wherein
the first units define the first hole regions, and
the second units define second hole region.

4. The semiconductor device of claim 1 , wherein
the thickness of the one of the plurality of first gates is the same as the thickness of the one of the plurality of second gates, and
the thickness of the one of the plurality of second interlayer insulating layers is thicker than the thickness of the one of the plurality of first interlayer insulating layers.

5. The semiconductor device of claim 1 , wherein
the ratio of the thickness of the one of the plurality of second interlayer insulating layers with respect to the thickness of the one of the plurality of second gates is greater than the ratio of the thickness of the one of the plurality of first interlayer insulating layers with respect to the thickness of the one of the plurality of first gates.

6. The semiconductor device of claim 1 , wherein
at least two of the plurality of second interlayer insulating layers have different thicknesses.

7. The semiconductor device of claim 6 , wherein the thickness of the one of the plurality of first gates and the thickness of the one of the plurality of second gates are the same.

8. The semiconductor device of claim 1 , wherein
the thickness of the one of the plurality of second gates is thinner than the thickness of the one of the plurality of first gates, and
the thickness of the one of the plurality of second interlayer insulating layers is thicker than the thickness of the one of the plurality of first interlayer insulating layers.

9. The semiconductor device of claim 1 , wherein the second units are closer to a lower surface of the stacked structure than to an upper surface of the stacked structure.

10. The semiconductor device of claim 1 , further comprising:
a semiconductor pattern inside the hole and below the vertical structure; and
a bit line on the stacked structure, wherein
the bit line is electrically connected to the vertical structure.

11. A semiconductor device comprising:
a substrate;
a stacked structure on the substrate,
the stacked structure including units stacked on top of each other in a direction perpendicular to a top surface of the substrate, the stacked structure including a hole passing through the stacked structure and having a bowing region,
the units including first units and a second unit between the first units,
each of the first units including a first gate and a first interlayer insulating layer on the first gate,
the second unit including a plurality of second gates and a plurality of second interlayer insulating layers alternately stacked on top of each other,
the second unit opposes at least a portion of the bowing region, and
a ratio of a thickness of one of the plurality of second interlayer insulating layers with respect to a thickness of one of the plurality of second gates is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate; and

a vertical structure in the hole.

12. The semiconductor device of claim 11 , wherein
the hole includes first hole regions defined by the first units,
the bowing region of the hole is between the first hole regions of the hole,
a width of the bowing region is greater than a width of the first hole regions adjacent to the bowing region, and
the first hole regions oppose the first units.

13. The semiconductor device of claim 11 , wherein the ratio of the thickness of the one of the plurality of second interlayer insulating layers with respect to the thickness of the one of the plurality of second gates is greater than the ratio of the thickness of the first interlayer insulating layer with respect to the thickness of the first gate.

14. The semiconductor device of claim 11 , wherein the one of the plurality of second interlayer insulating layers is thicker than the first interlayer insulating layer.

15. The semiconductor device of claim 11 , wherein the units further include a lower unit and an upper unit on the lower unit,
the first units and the second unit are between the lower unit and the upper unit,
the lower unit includes a lower gate and a lower interlayer insulating layer on the lower gate,
the upper unit includes an upper gate and an upper interlayer insulating layer on the upper gate, and
the upper interlayer insulating layer and the lower interlayer insulating layer are thicker than the first interlayer insulating layer and the one of the plurality of second interlayer insulating layers.

16. A semiconductor device comprising:
a substrate;
a stacked structure on the substrate,
the stacked structure including stacked regions stacked on top of each other in a direction perpendicular to a top surface of the substrate,
the stacked structure including a hole passing through the stacked structure,
the stacked regions including first stacked regions and second stacked region between the first stacked regions,
each of the first stacked regions including a plurality of first layers and a plurality of first interlayer insulating layers alternately stacked on top of each other,
the second stacked region including a plurality of second layers and a plurality of second interlayer insulating layers alternately stacked on top of each other, and

a ratio of a thickness of one of the plurality of second interlayer insulating layers with respect to a thickness of one of the plurality of second layers is different from a ratio of a thickness of one of the plurality of first interlayer insulating layers with respect to a thickness of one of the plurality of first layers,
the plurality of first layers and the plurality of second layers being a plurality of first gates and a plurality of second gates, respectively, or a plurality of first sacrificial layers and a plurality of second sacrificial layers, respectively; and
a vertical structure in the hole.

17. The semiconductor device of claim 16 , wherein
the plurality of first layers are is the plurality of first gates,
the plurality of second layers are the plurality of second gates, and
the hole in the stacked structure has a bowing region surrounded by at least some of the p

Assignees

• Lim Yeong Dae
• Jung Seung Jae
• Samsung Electronics Co Ltd

Inventors

• Lim Yeong Dae
• Jung Seung Jae

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic