Vertical type semiconductor devices and methods of manufacturing the same
US-2024172441-A1 · May 23, 2024 · US
Semiconductor memory device
US9018682B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018682-B2 |
| Application number | US-201314143077-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 30, 2013 |
| Priority date | Jun 12, 2013 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device, comprising: a substrate; a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate; a channel body provided inside a hole piercing the stacked body, the channel body extending in a stacking direction of the stacked body; and a memory portion provided between the channel body and each of the plurality of electrode layers; the hole having a large di…
Assignees
Inventors
Classifications
- H10D30/693Primary
Electricity · mapped topic
- H10D64/037Primary
Electricity · mapped topic
- H01L27/1052Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9018682B2 cover?
- According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D30/693. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).