Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit

Patent metadata

Field	Value
Publication number	US-10115727-B2
Application number	US-201715409818-A
Country	US
Kind code	B2
Filing date	Jan 19, 2017
Priority date	Jan 19, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

First claim

The invention claimed is:

1. A method for manufacturing a microelectronic circuit, comprising:
providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing the metal layer and the insulating layer of the memory transistor as parts of a MOS capacitor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing a gate contact connected to a metal layer of the capacitor of the memory transistor.

2. The method of claim 1 , comprising:
producing, from a lower metal layer, from a ferroelectric layer and from an upper metal layer, a ferroelectric capacitor as part of the memory transistor.

3. The method of claim 1 , comprising:
producing the at least one capacitor of the memory transistor on the insulating layer of the memory transistor.

4. The method of claim 1 , comprising:
producing layers of the transistor and layers of the memory transistor on the substrate in a front-end-of-line method.

5. The method of claim 1 , comprising:
producing, on the insulating layer of the transistor, an etch stop layer and a metal layer of the memory transistor in a common step.

6. The method of claim 1 , comprising:
producing, in a dielectric carrier, layers of the memory transistor and layers of the transistor.

7. The method of claim 1 , comprising:
producing, in a dielectric carrier, the transistor and the memory transistor with a back-end-of-line method, and
using an aluminum-BEoL method or a copper-BEoL method.

8. The method of claim 6 , comprising:
producing, in the dielectric carrier, a conductive path between the gate contacts and the transistor and the memory transistor, respectively.

9. The method of claim 6 , comprising:
producing the metal layer of the memory transistor as a conductive path in the dielectric carrier.

10. The method of claim 6 , comprising:
producing a further metal layer on the insulating layer and below the metal layer of the memory transistor, and producing an intermediate conductive path between the metal layer and the further metal layer in the dielectric carrier.

11. The method of claim 1 , wherein the at least one capacitor comprises a ferroelectric capacitor, the method comprising:
producing the ferroelectric capacitor with a smaller area than the MOS capacitor.

12. The method of claim 1 , wherein the at least one capacitor comprises a ferroelectric capacitor, the method comprising:
producing the ferroelectric capacitor with a smaller capacitance than the MOS capacitor.

13. The method of claim 1 , comprising:
producing the MOS capacitor as a FinFET.

14. The method of claim 1 , comprising:
forming the insulating layer of the memory transistor and the insulating layer of the transistor by a continuous layer.

15. The method of claim 1 , comprising:
forming a metal layer of the memory transistor and the metal layer of the transistor by a continuous layer.

16. The method of claim 1 , comprising:
performing the nitriding steps that may be used during manufacturing before producing the ferroelectric layer.

17. A method for manufacturing a microelectronic circuit, comprising:
providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor,
producing, on the insulating layer of the transistor, an etch stop layer and a metal layer of the memory transistor in a common step,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing a gate contact connected to a metal layer of the capacitor of the memory transistor.

18. A method for manufacturing a microelectronic circuit, comprising:
providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor,
producing a gate contact connected to a metal layer of the capacitor of the memory transistor,
producing, in a dielectric carrier, layers of the memory transistor and layers of the transistor, and
producing a further metal layer on the insulating layer and below the lower metal layer of the memory transistor, and producing an intermediate conductive path between the lower metal layer and the further metal layer in the dielectric carrier.

Assignees

• Fraunhofer Gessellschaft Zur Foerderung Der Angewandten Forschung E V
• Fraunhofer Ges Forschung

Inventors

• Mueller Johannes
• Polakowski Patrick
• Drescher Maximilian
• Riedel Stefan

Classifications

• H01L29/1087

  Electricity · mapped topic

• H01L27/10808

  Electricity · mapped topic

• H01L27/10894 Primary

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic