Solder metallization stack and methods of formation thereof

Patent metadata

Field	Value
Publication number	US-10115688-B2
Application number	US-201514726078-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming active circuitry and devices at a first semiconductor surface of a semiconductor substrate having a first side and an opposite second side, the first side having the first semiconductor surface, the second side having a second semiconductor surface;
providing a contact metal layer under the second semiconductor surface of the semiconductor substrate, the contact metal layer comprising aluminum, the second semiconductor surface being opposite to the first semiconductor surface, the contact metal layer physically contacting and covering all of the second semiconductor surface of the semiconductor substrate, the contact metal layer being provided at the second side of the semiconductor substrate;
at the second side, forming a diffusion barrier layer under the contact metal layer, wherein the diffusion barrier layer covers all of the contact metal layer and is a different material than the contact metal layer;
at the second side, forming an inert layer under the diffusion barrier layer, wherein the inert layer comprises a different material than the diffusion barrier layer;
at the second side, forming a solder active layer under the inert layer, wherein the inert layer comprises a different material than the solder active layer; and
at the second side, forming a conductive capping layer under the solder active layer,
wherein the contact metal layer, the diffusion barrier layer, the inert layer, the solder active layer, and the conductive capping layer form a solder metallization stack and wherein each layer in the solder metallization stack is coterminous with the second semiconductor surface of the semiconductor substrate.

2. The method of claim 1 , further comprising:
soldering by exposing the conductive capping layer to a solder material to form a solder layer over the inert layer.

3. The method of claim 1 , wherein the diffusion barrier layer comprises titanium or chromium.

4. The method of claim 1 , wherein the inert layer comprises tungsten titanium alloy.

5. The method of claim 1 , wherein the inert layer comprises tungsten, titanium nitride, tantalum, tantalum nitride, and chromium, wherein the solder active layer comprises nickel or nickel vanadium, and wherein the capping layer comprises silver.

6. The method of claim 1 , further comprising:
at the first side, providing a contact pad over the first semiconductor surface of the substrate;
at the first side, forming a front side diffusion barrier layer over the contact pad;
at the first side, forming a front side inert layer over the front side diffusion barrier layer;
at the first side, forming a front side solder active layer over the front side inert layer; and
at the first side, forming a front side capping layer over the front side solder active layer.

7. A method of forming a semiconductor device, the method comprising:
forming active circuitry and devices at a first semiconductor surface of a semiconductor substrate having a first side and an opposite second side, the first side having the first semiconductor surface, the second side having a second semiconductor surface;
providing a contact metal layer under the second semiconductor surface of the semiconductor substrate, the contact metal layer comprising aluminum, the second semiconductor surface being opposite to the first semiconductor surface, the contact metal layer physically contacting and covering all of the second semiconductor surface of the semiconductor substrate, the contact metal layer being provided at the second side of the semiconductor substrate;
at the second side, forming a first barrier layer physically contacting the contact metal layer, the first barrier layer covering all of the contact metal layer and being a different material than the contact metal layer;
at the second side, forming a second barrier layer under the first barrier layer, wherein the second barrier layer comprises a different material than the first barrier layer;
at the second side, forming a solder active layer under the second barrier layer, wherein the second barrier layer comprises a different material than the solder active layer, wherein the solder active layer is configured to be soldered with a solder material; and
forming a solder metallization stack comprising the contact metal layer, the diffusion barrier layer, the inert layer, the solder active layer, and the conductive capping layer, wherein each layer in the solder metallization stack is made coterminous with the second semiconductor surface of the semiconductor substrate.

8. The method of claim 7 , wherein the first barrier layer is a diffusion barrier layer for copper diffusion and the first barrier layer comprises titanium or chromium, and the second barrier layer comprises tungsten, titanium nitride, tantalum, tantalum nitride, or chromium.

9. The method of claim 7 , wherein the first barrier layer is a barrier to the diffusion of a first metal, and wherein the second barrier layer is a barrier to the diffusion of a second metal.

10. The method of claim 7 , wherein a diffusivity of a first metal in the first barrier layer is slower than a diffusivity of the first metal in the solder active layer.

11. The method of claim 10 , wherein the diffusivity of the first metal in the first barrier layer is slower than a diffusivity of the first metal in the second barrier layer.

12. The method of claim 10 , wherein a diffusivity of a second metal in the second barrier layer is slower than a diffusivity of the second metal in the solder active layer.

13. The method of claim 10 , wherein the diffusivity of the second metal in the second barrier layer is slower than a diffusivity of the second metal in the first barrier layer.

14. The method of claim 7 , further comprising:
forming a third barrier layer before forming the solder active layer.

15. The method of claim 14 , wherein a diffusivity of a first metal in the first barrier layer is slower than a diffusivity of the first metal in the solder active layer, wherein a diffusivity of a second metal in the second barrier layer is slower than a diffusivity of the second metal in the solder active layer, and wherein a diffusivity of a third metal in the third barrier layer is slower than a diffusivity of the third metal in the solder active layer.

16. A method of forming a semiconductor device, the method comprising:
forming active circuitry and devices at a first semiconductor surface of a semiconductor substrate having a first side and an opposite second side, the first side having the first semiconductor surface, the second side having a second semiconductor surface;
providing an aluminum layer under the second semiconductor surface of the semiconductor substrate, the second semiconductor surface being opposite to the first semiconductor surface, the aluminum layer covering all of the second semiconductor surface of the semiconductor substrate, the aluminum layer being provided at the second side of the semiconductor substrate, the aluminum layer physically contacting the semiconductor material of the semiconductor substrate;
at the second side, forming a titanium or chromium layer physically contacting the aluminum layer;
at the second side, forming a titanium-tungsten, titanium nitride, tantalum, tantalum nitride, or tungsten layer under the titanium or chromium layer, the titanium-tungsten, titanium nitride, tantalum, tantalum nitride, or tungsten layer physically contacting the titanium or chromium layer;
at the second side, forming a nickel or nickel vanadium lay

Assignees

• Infineon Technologies Ag

Inventors

• Karlovsky Kamil
• Napetschnig Evelyn
• Ehmann Michael
• Harrison Mark
• Pugatschow Anton

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title