Spectrally and temporally engineered processing using photoelectrochemistry

Patent metadata

Field	Value
Publication number	US-10115599-B2
Application number	US-201614988895-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Sep 28, 2012
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.

First claim

What is claimed is:

1. A method for fabricating a photodetector integral with a parabolic reflector, the method comprising:
a. photoelectroplating a top-contact metal-semiconductor-metal photodetector on a semiconductor wafer; and
b. defining a parabolic surface on the semiconductor wafer by
i. applying an etch solution to the surface of the semiconductor wafer;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor wafer; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination.

2. The method of claim 1 wherein the semiconductor wafer is silicon-on-insulator.

3. A method for fabricating a cell size sorting chip, the method comprising:
a. etching a concentric series of discrete height steps into a surface of a semiconductor substrate by
i. applying an etch solution to the surface of the semiconductor substrate;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor substrate; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination;

b. covering the surface of the semiconductor substrate with a platen having a substantially planar surface; and
c. mounting the semiconductor substrate and platen for centrally receiving a flux of cells suspended in a fluid and for rotation about a central axis.

4. A method for fabricating a cell size sorting chip, the method comprising:
a. etching a linear channel containing a series of discrete height steps into the surface of a semiconductor substrate by
i. applying an etch solution to the surface of the semiconductor substrate;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor substrate; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination;

b. covering the surface of the semiconductor substrate with a platen having a substantially planar surface; and
c. coupling microfluidic inlet and outlet tubes to the linear channel in such as manner as to provide for the flow of cells suspended in a fluid through the channel.

5. A method for fabricating a three-dimensional photonic bandgap chip, the method comprising:
a. growing a layered stack of triads of narrow bandgap, medium bandgap, and wide bandgap semiconductor with a top layer characterized by a center;
etching a periodic array of holes by
i. applying an etch solution to the surface of the semiconductor substrate;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor substrate; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination;

c. displaying a uniform pattern of light at an intermediate wavelength so as to cause lateral etching in exposed regions of selected layers, thereby forming a photonic crystal; and
d. illuminating through the center of the top surface causing absorption in the narrow bandgap material and creation of a defect cavity.

6. The method of claim 5 wherein the narrow bandgap semiconductor is GaAs.

Assignees

• Univ Illinois

Inventors

• Goddard Lynford
• Wang Kaiyuan
• Edwards Chris
• Edwards Lonna
• Yu Xin
• Liu Gang Logan
• Koker Terry

Classifications

• H10P50/648

  Anisotropic liquid etching · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P50/613

  of Group IV materials · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10P50/642 Primary

  Chemical etching · CPC title