Latency-optimized physical coding sublayer

Patent metadata

Field	Value
Publication number	US-10110335-B2
Application number	US-201615299193-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Jun 30, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio. Data is transmitted from the first clock domain to the second clock domain without buffering the data.

First claim

What is claimed is:

1. A system, comprising:
a media access control (MAC) sublayer configured to send data to a physical coding sublayer (PCS) utilizing a first clock domain operating at a first clock frequency; and
one or more physical medium attachment (PMA) lanes configured to transmit data utilizing a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio, and wherein transmitting data from the first clock domain to the second clock domain comprises determining, based on the fixed ratio, a first portion of a received data block to transmit during a clock cycle and a second portion of the received data block to delay transmitting until a subsequent clock cycle.

2. The system of claim 1 , further comprising:
a phase-locked loop (PLL) configured to generate the first clock frequency and the second clock frequency.

3. The system of claim 1 , further comprising:
two or more plesiochronous first-in, first-outs (FIFOs), each FIFO configured to receive data from a separate PMA lane in the second clock domain and further configured to synchronize the data in the PMA lanes.

4. The system of claim 1 , further comprising:
an asynchronous output FIFO configured to receive data from the second clock domain and output data in the first clock domain.

5. A computer program product for reducing latency, the computer program product comprising:
a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising:
computer-readable program code configured to receive data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency;
computer-readable program code configured to perform one or more functions in the PCS on the data in the first clock domain;
computer-readable program code configured to transmit the data on one or more physical medium attachment (PMA) lanes after performing one or more functions in the PCS, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio, and wherein transmitting data from the first clock domain to the second clock domain comprises determining, based on the fixed ratio, a first portion of a received data block to transmit during a clock cycle and a second portion of the received data block to delay transmitting until a subsequent clock cycle; and
computer-readable program code configured to perform one or more functions in the PCS on the data in the second clock domain.

6. The computer program product of claim 5 , further comprising:
computer-readable program code configured to transmit the data to an asynchronous output first-in, first-out (FIFO) located in the first clock domain after performing one or more functions on the data in the second clock domain.

7. The computer program product of claim 5 , further comprising:
computer-readable program code configured to transmit data from a transmit side of the PCS to a receive side of the PCS via one or more PMA lanes.

8. The computer program product of claim 7 , wherein the data is received from the one or more PMA lanes in one or more plesiochronous input FIFOs on the receive side of the PCS.

Assignees

• IBM

Inventors

• Basso Claude
• Song Cheng Wei
• Verplanken Fabrice Jean

Classifications

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L7/06

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title

• H04L47/6245

  Modifications to standard FIFO or LIFO · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title