Latency-optimized physical coding sublayer

Patent metadata

Field	Value
Publication number	US-9515817-B2
Application number	US-201414445294-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Jun 30, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Method and apparatus for reducing latency in a networking application comprises receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further comprises performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio. The method also comprises performing one or more functions in the PCS on the data in the second clock domain.

First claim

What is claimed is:

1. A method comprising:
receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency;
performing one or more functions in the PCS on the data in the first clock domain;
after performing one or more functions in the PCS, transmitting the data on one or more physical medium attachment (PMA) lanes coupled to the PCS, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio, wherein the fixed ratio between the first clock frequency and the second clock frequency is 32:33, and wherein the data is transmitted from the first clock domain to the second clock domain without buffering the data; and
performing one or more functions in the PCS on the data in the second clock domain.

2. The method of claim 1 , wherein performing one or more functions on the data in the first clock domain comprises encoding and scrambling the data to create one or more 66-bit blocks.

3. The method of claim 1 , further comprising:
after performing one or more functions on the data in the second clock domain, transmitting the data to an asynchronous output first-in, first-out (FIFO) located in the first clock domain in the PCS.

4. The method of claim 1 , wherein performing one or more functions on the data in the first clock domain comprises inserting one or more alignment markers in the data.

5. The method of claim 4 , wherein performing one or more functions on the data in the second clock domain comprises removing one or more alignment markers in the data.

6. The method of claim 1 , further comprising transmitting data from a transmit side of the PCS to a receive side of the PCS via one or more PMA lanes.

7. The method of claim 6 , wherein the data is received from the one or more PMA lanes in one or more plesiochronous input FIFOs on the receive side of the PCS.

8. The method of claim 7 , wherein the data in a subset of the plesiochronous input FIFOs is synchronized to the data in one of the plesiochronous input FIFOs that is designated as a master.

9. The method of claim 1 , wherein performing one or more functions on the data in the second clock domain comprises deskewing the data.

10. A method comprising:
receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency;
performing one or more functions in the PCS on the data in the first clock domain;
after performing one or more functions in the PCS, transmitting the data on one or more physical medium attachment (PMA) lanes coupled to the PCS, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio, and wherein the fixed ratio between the first clock frequency and the second clock frequency is 32:33; and
performing one or more functions in the PCS on the data in the second clock domain.

Assignees

• IBM

Inventors

• Basso Claude
• Song Cheng Wei
• Verplanken Fabrice Jean

Classifications

• H04L47/6245

  Modifications to standard FIFO or LIFO · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title

• H04L7/06 Primary

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title

• H04L1/0018

  based on latency requirement · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title