Electronic device including a semiconductor memory and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016013405-A1
Application number	US-201514599234-A
Country	US
Kind code	A1
Filing date	Jan 16, 2015
Priority date	Jul 9, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

The disclosed technology provides semiconductor memory devices and applications in electronic devices. In one implementation, an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.

First claim

1 . An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a substrate; a first contact plug formed over the substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer formed over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance; and a second electrode layer formed over the variable resistance layer.

2 . The electronic device of claim 1 , wherein the second portion includes a structure identical to the first portion but are added with impurities which cause a loss of the variable resistance.

3 . The electronic device of claim 1 , wherein the variable resistance layer includes a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and
the second portion includes impurities which cause a loss of a magnetic characteristic in the first and second magnetic layers.

4 . The electronic device of claim 3 , wherein the impurities include Ga, Ge, As, In, P, C, Si, N or B.

5 . The electronic device of claim 1 , wherein:
the variable resistance layer includes a metal oxide, and the second portion contains more oxygen than the first portion.

6 . The electronic device of claim 1 , wherein the second portion satisfies a stoichiometric ratio.

7 . The electronic device of claim 1 , wherein the second electrode layer includes a lower portion having a sidewall and a bottom surface which are surrounded by the variable resistance layer, and an upper portion located over the lower portion and having a width greater than a width of the lower portion, and
portions of the first electrode layer and the variable resistance layer which are provided over the interlayer dielectric layer are aligned on their sides with a sidewall of the upper portion of the second electrode layer.

8 . The electronic device of claim 7 , wherein the variable resistance layer which is located over the interlayer dielectric layer has a portion in which the variable resistance does not exist.

9 . The electronic device of claim 1 , wherein top surfaces of the first electrode layer, the variable resistance layer and the second electrode layer are located at a same level as a top surface of the interlayer dielectric layer.

10 . The electronic device of claim 1 , wherein the semiconductor memory further includes:
a second contact plug coupled to a top surface of the second electrode layer.

11 . The electronic device of claim 1 , wherein the first portion is switched between different resistance states according to a voltage or current supplied through the first electrode layer coupled to an outer sidewall of the first portion and the second electrode layer coupled to an inner sidewall of the first portion.

12 . The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

13 . An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a substrate having a conductive layer; an interlayer dielectric layer located over the substrate and having a hole which exposes the conductive layer; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the conductive layer; a variable resistance layer formed over the first electrode layer and including an insulating portion which is parallel to the bottom surface of the hole; and a second electrode layer formed over the variable resistance layer.

14 . The electronic device of claim 13 , wherein the variable resistance layer includes a first magnetic layer, a second magnetic layer, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and
the insulating portion include impurities which cause a loss of magnetic characteristics in the first and second magnetic layers.

15 . The electronic device of claim 14 , wherein the impurities include Ga, Ge, As, In, P, C, Si, N or B.

16 . The electronic device of claim 13 , wherein the variable resistance layer includes a metal oxide, and
the insulating portion contains more oxygen than a remaining portion of the variable resistance layer.

17 . The electronic device of claim 16 , wherein the insulating portion satisfies a stoichiometric ratio.

18 . The electronic device of claim 13 , wherein the first electrode layer is further provided over the interlayer dielectric layer, and
the variable resistance layer further includes an additional insulating portion which is provided over the interlayer dielectric layer.

19 . The electronic device of claim 18 , wherein the second electrode layer includes a lower portion having a sidewall and a bottom surface which are surrounded by the variable resistance layer, and an upper portion located over the lower portion and having a width greater than a width of the lower portion, and
sidewalls of portions of the variable resistance layer and the first electrode layer which are located over the interlayer dielectric layer are aligned with a sidewall of the upper portion of the second electrode layer.

20 . The electronic device of claim 1 , wherein the first and second portions of the variable resistance layer are formed of an identical structure which exhibits the variable resistance but are different in that the second portion includes impurities which cause a loss of the variable resistance while the first portion is substantially free of the impurities and thus maintains the variable resistance.

Assignees

• Sk Hynix Inc

Inventors

• Kim In-Hoe

Classifications

• H01L45/145 Primary

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title