Process for fabricating a field effect transistor having a coating gate

Patent metadata

Field	Value
Publication number	US-10109735-B2
Application number	US-201715730923-A
Country	US
Kind code	B2
Filing date	Oct 12, 2017
Priority date	Oct 13, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.

First claim

The invention claimed is:

1. A process for fabricating a gate-wrap-around field-effect transistor, comprising:
providing a substrate surmounted with a superposition of first to third nanowires each having a median portion and first and second ends on either side of the median portion along a longitudinal axis thereof, each of the nanowires being made of a semiconductor, said second nanowire being disposed between the first and the third nanowires and being made of a semiconductor that is different from the semiconductor of the first nanowire and different from the semiconductor of the third nanowire, so that the second nanowire is subjected to a mechanical strain along its longitudinal axis, the median portion of the first to third nanowires being covered by a sacrificial gate;
forming voids by removing a portion of the first and the third nanowires that is intermediate between their respective first end and their respective median portion, and by removing a portion of the first and the third nanowires that is intermediate between their respective second end and their respective median portion, while preserving the superposition of the first to the third nanowires level with the first and the second ends and under the sacrificial gate;
forming an electrical insulator in said formed voids and around the second nanowire;
removing the sacrificial gate and removing the median portion of the first and the third nanowires; and
forming a gate electrode wrapped around the median portion of the second nanowire.

2. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the removing of the intermediate portions of the first and the third nanowires comprises a step of implanting ions into these intermediate portions and then a step of selectively etching these portions.

3. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the removing of the intermediate portions of the first and the third nanowires comprises etching the intermediate portions of the first and the third nanowires according to their crystal planes.

4. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the first to the third provided nanowires include silicon, and the first and the third nanowires include a proportion of germanium higher than that of the second nanowire.

5. The process for fabricating a gate-wrap-around field-effect transistor, according to claim 4 , wherein the first and the third provided nanowires are made of Si (1-x) Ge x , where 0.2<x<0.6.

6. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , further comprising a step of doping the second nanowire in a portion that is intermediate between its first end and its median portion and in a portion that is intermediate between its second end and its median portion, after the step of providing the substrate and before the step of removing the sacrificial gate.

7. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , further comprising, between the step of forming the electrical insulator and the step of removing the sacrificial gate, the steps of:
removing the first and the second ends of the first and the third nanowires; and
depositing a semiconductor that is different from that of the first to the third nanowires, by epitaxial growth from the first and the second ends of the second nanowire, so as to increase an amplitude of the mechanical strain in the median portion of the second nanowire.

8. The process for fabricating a gate-wrap-around field-effect transistor according to claim 7 , wherein the material deposited by epitaxial growth is SiC doped in situ with phosphorus.

9. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the first to the third provided nanowires have a thickness at most equal to 15 nm.

10. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the provided substrate includes sacrificial spacers covering a portion of the first to the third nanowires on either side of the sacrificial gate, the process further comprising a step of removing the sacrificial spacers prior to the forming of the voids.

11. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , wherein the removed portions of the first and the third nanowires each have a length comprised between 3 nm and 15 nm.

12. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1 , further comprising a step of forming spacers wrapped around the electrical insulator on either side of the median portion of the second nanowire.

Assignees

• Commissariat Energie Atomique

Inventors

• Coquand Remi
• Augendre Emmanuel
• Reboh Shay

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title