Integrated circuits with fets having nanowires and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016254382-A1
Application number	US-201514633351-A
Country	US
Kind code	A1
Filing date	Feb 27, 2015
Priority date	Feb 27, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

First claim

1 . A method of forming an integrated circuit comprising:
forming a stack overlying a substrate, wherein the stack comprises a silicon germanium layer and a silicon layer, wherein the silicon germanium layer has a first germanium concentration; condensing the stack to produce a second germanium concentration in the silicon germanium layer, wherein the second germanium concentration is greater than the first germanium concentration; forming a fin that includes the stack; and forming a gate overlying the fin.

2 . The method of claim 1 wherein condensing the stack comprises producing the second germanium concentration of from about 70 weight percent to about 90 weight percent germanium based on the total weight of the silicon germanium layer.

3 . The method of claim 2 wherein condensing the stack comprises increasing a germanium concentration from the first germanium concentration of about 20 to about 50 weight percent based on the total weight of the silicon germanium layer to the second germanium concentration.

4 . The method of claim 1 wherein condensing the stack comprises heating the stack to about 900 to about 1,100 degrees centigrade for about 0.5 to about 1.5 hours.

5 . The method of claim 1 wherein forming the gate overlying the fin comprises forming a replacement metal gate overlying the fin; the method further comprising
forming a source and a drain electrically coupled to the silicon germanium layer in the fin.

6 . The method of claim 5 further comprising:
forming an interface insulating layer before forming the replacement metal gate, wherein the interface insulating layer is positioned between the fin and the replacement metal gate.

7 . The method of claim 6 further comprising:
forming a gate dielectric layer overlying the interface insulating layer such that the gate dielectric layer is positioned between the interface insulating layer and the replacement metal gate.

8 . The method of claim 1 further comprising:
forming a nanowire insulator from the silicon layer.

9 . The method of claim 8 wherein forming the nanowire insulator comprises oxidizing silicon in the silicon layer to form silicon dioxide.

10 . The method of claim 1 wherein condensing the stack comprises condensing the stack in an oxygen ambient.

11 . The method of claim 1 further comprising:
inducing a compressive strain on the silicon germanium layer.

12 . A method of fabricating a nanowire comprising:
epitaxially forming a stack over a substrate, wherein the stack comprises a silicon germanium layer and a silicon layer, and wherein the silicon germanium layer has a first silicon germanium layer volume; condensing the stack to produce a second silicon germanium layer volume less than the first silicon germanium layer volume; and forming a nanowire from the silicon germanium layer.

13 . The method of claim 12 wherein condensing the stack comprises changing a first germanium concentration before condensing the stack to a second germanium concentration after condensing the stack in the silicon germanium layer, wherein the first germanium concentration is from about 20 to about 50 weight percent germanium, and the second germanium concentration is from about 70 weight percent to about 90 weight percent germanium.

14 . The method of claim 12 wherein condensing the stack comprises:
migrating silicon from the silicon germanium layer into the silicon layer.

15 . The method of claim 14 wherein the silicon layer has a first silicon layer volume before condensing the stack, and wherein condensing the stack comprises:
producing a second silicon layer volume after condensing the stack that is larger than the first silicon layer volume.

16 . The method of claim 12 further comprising:
forming a fin, wherein the fin comprises the nanowire formed from the silicon germanium layer and the fin comprises the silicon layer, wherein the silicon layer comprises silicon dioxide after condensing the stack; and
forming a replacement metal gate overlying the fin.

17 . The method of claim 16 further comprising:
forming an interface insulating layer overlying the fin; and
forming a gate dielectric layer overlying the interface insulating layer such that the gate dielectric layer is positioned between the interface insulating layer and the replacement metal gate.

18 . The method of claim 12 wherein condensing the stack comprises condensing the stack at a temperature of from about 900 to about 1,100 degrees centigrade.

19 . The method of claim 12 further comprising:
inducing a compressive strain on the nanowire.

20 . An integrated circuit comprising:
a fin; a gate overlying the fin; a nanowire within the fin, wherein the nanowire comprises germanium with a germanium concentration of from about 70 weight percent to about 90 weight percent; a nanowire insulator overlying the nanowire, wherein the nanowire insulator comprises silicon dioxide; and a gate dielectric layer between the fin and the gate.

Assignees

• Globalfoundries Inc

Inventors

• Hoentschel Jan
• Flachowsky Stefan
• Zschaetzsch Gerd

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title