Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device

Patent metadata

Field	Value
Publication number	US-9293587-B2
Application number	US-201313948374-A
Country	US
Kind code	B2
Filing date	Jul 23, 2013
Priority date	Jul 23, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

First claim

What is claimed is:

1. A device comprising:
a gate structure formed over a finned substrate;
an embedded source and a drain (S/D) adjacent the gate structure and adjacent a fin of the finned substrate; and
an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

2. The device of claim 1 , wherein the epi bottom region comprises an implanted region beneath an upper portion of the epi bottom region, wherein the implanted region is doped and the upper portion of the epi bottom region is undoped.

3. The device of claim 2 , wherein the embedded S/D is doped.

4. The device of claim 3 , the embedded S/D comprising P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor and N++ Silicon Carbon (SiC) for a n-channel metal-oxide-semiconductor field-effect transistor.

5. The device according to claim 1 , further comprising an isolation oxide beneath an active fin channel of the gate structure.

6. The device according to claim 1 , the embedded S/D comprising embedded SiGe.

7. A fin field effect transistor (FinFET) device having isolated source and drain regions, the FinFET device comprising:
a gate structure formed over a finned substrate;
an isolation oxide beneath an active fin channel of the gate structure;
an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and
an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

8. The FinFET device of claim 7 , wherein the epi bottom region comprises an implanted region beneath an upper portion of the epi bottom region, wherein the implanted region is doped and the upper portion of the epi bottom region is undoped.

9. The FinFET device of claim 8 , wherein the embedded S/D is doped.

10. The device of claim 9 , the embedded S/D comprising P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor and N++ Silicon carbon (SiC) for a n-channel metal-oxide-semiconductor field-effect transistor.

11. The device according to claim 7 , the embedded S/D comprising embedded SiGe.

12. A method for isolating source and drain regions of a fin field effect transistor (FinFET) device, the method comprising:
forming a gate structure over a finned substrate;
providing an isolation oxide beneath an active fin channel of the gate structure;
forming an embedded source and a drain (S/D) adjacent the gate structure and the isolation oxide; and
forming an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

13. The method of claim 12 , further comprising implanting a set of implanted regions beneath an upper portion of the epi bottom region, wherein the implanted region is doped and the upper portion of the epi bottom region is undoped.

14. The method of claim 13 , further comprising doping the embedded S/D.

15. The method of claim 14 , the embedded S/D comprising P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor.

16. The method according to claim 12 , the embedded S/D comprising embedded SiGe.

17. The method according to claim 12 , further comprising:
forming a set of fins from a bulk Si;
depositing a shallow trench isolation (STI) material over the set of fins;
recessing the STI material to expose the set of fins; and
forming a spacer over each of the set of fins.

18. The method according to claim 17 , further comprising performing a thermal oxidation to the FinFET device following deposition of the STI material over the set of fins.

19. The method according to claim 17 , the forming the set of fins comprising:
forming an epi SiGe layer over the bulk Si;
forming an epi Si layer over the epi SiGe; and
patterning a set of openings through the epi Si layer and the epi SiGe layer, and into the bulk silicon.

20. The method according to claim 17 , the forming the set of fins from the substrate comprising:
patterning a set of openings into the bulk Si;
forming a SiN capping layer over each of the set of fins; and
etching the bulk Si between each of the set of fins.

Assignees

• Globalfoundries Inc

Inventors

• Jacob Ajey Poovannummoottil
• Akarvardar Murat K

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H01L29/66795

  Electricity · mapped topic