Methods and apparatus for three-dimensional nonvolatile memory

Patent metadata

Field	Value
Publication number	US-10109680-B1
Application number	US-201715622100-A
Country	US
Kind code	B1
Filing date	Jun 14, 2017
Priority date	Jun 14, 2017
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.

First claim

The invention claimed is:

1. A method comprising:
forming a word line layer above a substrate, the word line layer disposed in a first direction;
forming a dielectric material above a substrate;
forming a hole in the dielectric material, the hole disposed in a second direction perpendicular to the first direction;
forming a nonvolatile memory material in the hole, the nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, wherein the barrier material layer comprises an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.;
forming a bit line in the hole; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line layer.

2. The method of claim 1 , wherein the barrier material layer has a thickness between about 0.5 nm and about 4 nm.

3. The method of claim 1 , wherein the barrier material layer comprises an oxide.

4. The method of claim 1 , wherein the barrier material layer comprises one or more of cerium-doped zirconium oxide, cerium oxide, gadolinium doped ceria, hafnium oxide, lanthanum oxide, lanthanum cobalt oxide, lanthanum gallium oxide, lanthanum germanium oxide, lanthanum manganese oxide, lanthanum molybdenum oxide, lanthanum silicon oxide, lanthanum-doped titanium oxide, praseodymium calcium manganese oxide, scandium-stabilized zirconia, strontium titanate, tantalum oxide, and yttria-stabilized zirconia.

5. The method of claim 1 , wherein forming the barrier material layer comprises forming the barrier material layer by one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and atomic layer deposition nanolaminates.

6. The method of claim 1 , wherein the semiconductor material layer comprises one or more of carbon, germanium, silicon, tantalum nitride, and tantalum silicon nitride.

7. The method of claim 1 , wherein the conductive oxide material layer comprises one or more of aluminum-doped zinc oxide, aluminum-doped zirconium oxide, cerium oxide, indium tin oxide, niobium-doped strontium titanate, praseodymium calcium manganese oxide, titanium oxide, tungsten oxide, and zinc oxide.

8. A method of forming a monolithic three-dimensional memory array, the method comprising:
forming a stack of conductive material layers above a substrate;
etching the stack of conductive material layers to form a row of conductive material layers;
forming a dielectric material adjacent the row of conductive material layers;
forming a hole in the dielectric material, the hole disposed adjacent the row of conductive material layers;
forming on a sidewall of the hole a nonvolatile memory material comprising a semiconductor material layer and a conductive oxide material layer;
forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, wherein the barrier material layer comprises an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.;
forming a bit line in the hole; and
forming an array of memory cells, each memory cell comprising the nonvolatile memory material at an intersection of the bit line and the conductive material.

9. The method of claim 8 , wherein the barrier material layer has a thickness between about 0.5 nm and about 4 nm.

10. The method of claim 8 , wherein the barrier material layer comprises one or more of cerium-doped zirconium oxide, cerium oxide, gadolinium doped ceria, hafnium oxide, lanthanum oxide, lanthanum cobalt oxide, lanthanum gallium oxide, lanthanum germanium oxide, lanthanum manganese oxide, lanthanum molybdenum oxide, lanthanum silicon oxide, lanthanum-doped titanium oxide, praseodymium calcium manganese oxide, scandium-stabilized zirconia, strontium titanate, tantalum oxide, and yttria-stabilized zirconia.

Assignees

• Sandisk Technologies Llc

Inventors

• Wicklein Sebastian J M
• Saenz Juan P
• Ranganathan Srikanth
• Wu Ming-Che
• Kumar Tanmay

Classifications

• H01L45/148

  Electricity · mapped topic

• H01L45/1246

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• G11C2213/34

  Material includes an oxide or a nitride · CPC title

• G11C2213/35

  Material including carbon, e.g. graphite, grapheme · CPC title