Double-masking technique for increasing fabrication yield in superconducting electronics

Patent metadata

Field	Value
Publication number	US-10109673-B2
Application number	US-201715456010-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Sep 20, 2006
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

First claim

What is claimed is:

1. An integrated circuit based on a plurality of Nb-based Josephson junctions, comprising:
a Josephson junction trilayer comprising a lower Nb-containing superconductive layer, an insulating layer, an upper Nb-containing superconductive layer, and sidewalls thereof, on a substrate, fabricated into at least one Josephson junction having a defined junction area less than 1 square micron, the at least one Josephson junction comprising an anodized double oxide layer of AlOx on top of NbOx, wherein the double oxide is patterned in a vacuum processing chamber using a dry etch process to provide a structure surrounding the defined junction comprising a continuous NbOx layer which extends vertically along the sidewalls of the lower Nb-containing superconductive layer, the insulating layer, and the upper Nb-containing superconductive layer; and
a silicon dioxide layer formed directly on top of the upper Nb-containing superconductor layer.

2. The integrated circuit of claim 1 , wherein the dry etch process comprises ion milling with a neutral beam of argon atoms.

3. The integrated circuit of claim 1 , wherein the dry etch process comprises the two sequential steps of:
using a chlorine-based plasma etch to remove the top layer of AlOx; and
using a fluorine-based plasma etch to remove the bottom layer of NbOx.

4. The integrated circuit of claim 1 , wherein the defined junction area comprises a layer of photoresist on top of the silicon dioxide, wherein the photoresist has a higher adhesion for the silicon dioxide than the upper Nb-containing superconductive layer.

5. The integrated circuit of claim 1 , wherein the Josephson junction trilayer comprises a sequence of Nb, Al, AlOx, and Nb, wherein the AlOx layer is between 1-2 nm thick.

6. The integrated circuit of claim 1 , wherein the at least one Josephson junction comprises at least one thousand Josephson junctions.

7. The integrated circuit of claim 6 , wherein the at least one thousand Josephson junctions each have operating superconducting critical currents that are within about 1% of a respective design specification.

8. The integrated circuit of claim 6 , wherein the integrated circuit comprises a plurality of functional circuits, each configured to operate at clock frequency of at least 100 GHz.

9. The integrated circuit of claim 1 , wherein the integrated circuit comprises at least one functional circuit configured to operate at clock frequency of at least 100 GHz.

10. A Josephson junction integrated circuit, produced by a process comprising:
depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate;
depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD);
depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer;
patterning the photoresist;
etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer;
anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, to thereby increase a layer thickness of the anodized insulating layer and the portion of the lower superconductor layer, with respect to the insulating layer and the portion of the lower superconductor layer, to create a continuous anodized portion of the lower superconductor layer which surrounds and extends vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer, and which interrupts the anodized insulating layer; and
dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device.

11. The Josephson junction circuit according to claim 10 , further comprising removing the photoresist.

12. The Josephson junction circuit according to claim 10 , wherein the dry etching comprises ion-milling with a neutral beam of argon (Ar) atoms.

13. The Josephson junction circuit according to claim 10 , wherein the dry etching comprises plasma etching with a chlorine-based plasma and then a fluorine-based plasma.

14. The Josephson junction circuit according to claim 13 , wherein the dry etching comprises reactive ion etching.

15. The Josephson junction circuit according to claim 13 , wherein the dry etching comprises an inductively coupled plasma etching.

16. The Josephson junction circuit according to claim 10 , wherein the lower superconductor layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductor layer comprises niobium.

17. The Josephson junction circuit according to claim 10 , wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm.

18. A method of forming a Josephson junction integrated circuit, comprising:
depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate;
depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD);
depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer; patterning the photoresist;
etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer;
anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, creating a continuous anodized portion of the lower superconductor layer surrounding and extending vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer of a defined junction and causing a discontinuity of the anodized insulating layer between the insulating layer and the anodized insulating layer; and
dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device.

19. The method according to claim 18 , wherein the integrated circuit is patterned to define a plurality of interconnected Josephson junctions formed, further comprising operating the plurality of Josephson junctions at a clock rate of at least 100 GHz.

20. The method according to claim 18 ,
wherein the lower superconductor layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductor layer comprises niobium;
wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm; and
wherein the dry etching comprises at least one of:
ion-milling with a neutral beam of argon (Ar) atoms;
inductively coupled plasma etching with a chlorine-based plasma and then a fluorine-based plasma; and
reactive ion etching.

Assignees

• Hypres Inc

Inventors

• Tolpygo Sergey K

Classifications

• H01L39/12

  Electricity · mapped topic

• H01L27/18 Primary

  Electricity · mapped topic

• H01L39/223

  Electricity · mapped topic

• H01L39/2493

  Electricity · mapped topic

• H01L39/025

  Electricity · mapped topic