Double-masking technique for increasing fabrication yield in superconducting electronics

Patent metadata

Field	Value
Publication number	US-9595656-B2
Application number	US-201514850634-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Sep 20, 2006
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

First claim

What is claimed is:

1. A method of forming a superconducting integrated circuit, comprising:
forming an adhesion layer formed directly on top of an upper superconductor layer of a Josephson junction trilayer comprising the upper superconductor, an insulating layer, and a lower superconductor;
forming and patterning a resist layer directly on top of the adhesion layer, to expose portions of the adhesion layer through the resist layer and form resist layer edges;
exposing portions of the insulating layer corresponding to patterning of the resist layer by etching through the exposed portions of the adhesion layer and through the upper superconductor layer;
anodizing portions of the lower superconducting layer underlying the exposed portions of the insulating layer in an anodization solution, to selectively form circuit patterns comprising Josephson junction circuit elements under unexposed portions of the adhesion layer, the anodized portions of the lower superconductor layer being volumetrically expanded with respect to the non-anodized portions of the lower superconductor layer to form a layer of anodized superconductor on exposed sidewalls of the upper superconductor and insulating layer, inducing stresses on the adjacent resist layer edges; and
preventing peeling of the resist layer and leeching of etching solution under the resist layer subject to the anodization-induced stresses on the adjacent resist layer edges, by adhesion of the adhesion layer to the resist layer,
wherein in an absence of the adhesion layer with direct deposition of the resist layer on the upper superconductor layer, the resist layer would peel from the upper superconductor layer and the anodization solution would leech under the resist layer, causing fabrication defects, and
wherein the adhesion layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects of the adhesion layer during the anodizing.

2. The method according to claim 1 , wherein the adhesion layer comprises silicon dioxide.

3. The method according to claim 1 , wherein the lower superconductor layer comprises niobium.

4. The method according to claim 1 , wherein the insulating layer comprises aluminum oxide formed by oxidizing a layer of aluminum formed on the lower superconductor layer prior to deposition of the upper superconductor layer, wherein a portion of the lower superconductor layer is anodized through the aluminum oxide.

5. The method according to claim 1 , wherein the Josephson junction trilayer comprises a lower layer of niobium, an insulating layer comprising aluminum oxide, and an upper layer of niobium.

6. The method according to claim 1 , wherein the adhesion layer comprises sputtered or plasma enhanced chemical vapor deposition-deposited SiO 2 .

7. The method according to claim 1 , wherein the resist comprises UVN®-30 negative photoresist.

8. The method according to claim 1 , wherein the adhesion layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm.

9. The method according to claim 1 , wherein the adhesion layer is formed by a sputtering process with a layer thickness of between about 5-300 nm.

10. The method according to claim 1 , wherein the patterns comprising Josephson junction circuit elements circuit comprise at least two separately operating Josephson junctions.

11. A method of forming an integrated circuit having Josephson junctions, comprising:
forming a Josephson junction trilayer comprising an upper superconductor, an insulating layer, and a lower superconductor on a substrate;
depositing an adhesion layer directly on top of the upper superconductor;
forming a resist layer directly on top of the adhesion layer;
patterning and developing the resist layer, to expose portions of the adhesion layer through the resist layer;
etching the exposed portions of the adhesion layer through the upper superconductor to expose the insulating layer;
selectively anodizing portions of the lower superconductor under the exposed portions of the insulating layer, to selectively form Josephson junction circuit elements under remaining portions of the adhesion layer and the resist layer, wherein the anodized portions of the lower superconductor increase in volume with respect to the non-anodized portions under remaining portions of the resist layer and grow beyond the insulating layer to form a layer of anodized lower superconductor on an exposed sidewall of the upper superconductor, the increase in volume inducing stresses on the resist layer at a patterned edge of the resist layer, the adhesion layer having sufficient adhesion to the resist layer and to the upper superconductor to maintain adhesion when subject to the stresses; and
removing at least a portion of the exposed portions of the insulating layer and the anodized portions of the lower superconductor to expose the lower superconductor,
wherein the adhesion layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects during the anodizing.

12. The method according to claim 11 , wherein the Josephson junction trilayer is formed on a silicon substrate and the adhesion layer comprises silicon dioxide.

13. The method according to claim 11 , wherein the Josephson junction circuit elements comprise at least two separately operating Josephson junctions having submicron feature sizes.

14. The method according to claim 11 , wherein the lower superconductor comprises niobium, the insulating layer comprises aluminum oxide, and the upper superconductor comprises niobium.

15. The method according to claim 1 , wherein the resist layer comprises UVN®-30 negative photoresist.

16. The method according to claim 1 , wherein the adhesion layer comprises a dielectric, and the resist comprises at least one of an electron beam exposed resist and a photoresist.

17. The method according to claim 1 , wherein the adhesion layer is formed by chemical vapor deposition or sputtering of SiO 2 with a layer thickness of between about 5-300 nm.

18. A method for fabrication of an integrated circuit having Josephson junctions, comprising the steps of:
providing a substrate, having a Josephson junction trilayer thereon comprising a lower superconducting layer, an insulating layer, and an upper superconducting layer, the upper superconducting layer being directly covered by an intermediate layer comprising a dielectric having a thickness of at least 5 nm, which in turn is directly covered by a resist layer;
selectively patterning portions of the resist layer in dependence on an irradiation pattern, and developing the pattered portions of the resist layer to expose portions of the intermediate layer;
etching the exposed portions of the intermediate layer and underlying portions of the upper superconducting layer, substantially without removing remaining portions of the resist layer, to expose the insulating layer, to thereby form a bilayer anodization mask comprising the resist layer and the intermediate layer; and
anodizing the exposed insulating layer and underlying lower superconducting layer through the bilayer mask cause a volumetric increase in at least the lower superconducting layer, such that anodized superconductor of the lower superconductor layer volumetrically expands above the intermediate layer, and stresses are induced in the resist layer, to selectively form Josephson junction circuit elements comprising intact portions of the Josephson junction trilayer protected by the bilayer mask, wherein the resist layer remains strongly adherent to t

Assignees

• Hypres Inc
• Hypres Inc

Inventors

• Tolpygo Sergey K

Classifications

• H01L39/249

  Electricity · mapped topic

• H01L27/18

  Electricity · mapped topic

• H01L39/223

  Electricity · mapped topic

• H01L39/12

  Electricity · mapped topic

• H01L39/2493 Primary

  Electricity · mapped topic