Double-sided circuit

Patent metadata

Field	Value
Publication number	US-10103703-B2
Application number	US-201615161138-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	May 20, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

First claim

What is claimed is:

1. A circuit apparatus, comprising:
an insulator having a first surface, a second surface, and a periphery;
a first subset of circuit elements disposed directly on the first surface, wherein the first subset of circuit elements includes a first inductor and a first capacitor;
a second subset of circuit elements disposed directly on the second surface, wherein the second subset of circuit elements includes a second inductor and a second capacitor; and
at least one conductive sidewall disposed on the periphery, wherein the at least one conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

2. The circuit apparatus of claim 1 , wherein:
the insulator includes glass; and
a thickness of the insulator is greater than a thickness of the first subset of circuit elements and greater than a thickness of the second subset of circuit elements.

3. The circuit apparatus of claim 1 , wherein the first subset of circuit elements are configured to filter a first frequency band and the second subset of circuit elements are configured to filter a second frequency band, the second frequency band being higher than the first frequency band.

4. The circuit apparatus of claim 1 , wherein the second inductor has a lower inductance than the first inductor and the second capacitor has a lower capacitance than the first capacitor.

5. The circuit apparatus of claim 4 , wherein the first inductor is a first spiral inductor and the second inductor is a second spiral inductor.

6. The circuit apparatus of claim 4 , wherein the circuit apparatus further comprises a first middle insulator on the first surface of the insulator and a second middle insulator on the second surface of the insulator, and wherein:
the first inductor includes a first inner conductive sublayer in contact with the first middle insulator, a first insulative sublayer in contact with the first inner conductive sublayer, and a first outer conductive sublayer in contact with the first insulative sublayer; and
the second inductor includes a second inner conductive sublayer in contact with the second middle insulator, a second insulative sublayer in contact with the second inner conductive sublayer, and a second outer conductive sublayer in contact with the second insulative sublayer.

7. The circuit apparatus of claim 4 , wherein:
the first capacitor includes a first inner conductive layer in contact with the first surface of the insulator, a first dielectric layer in contact with the first inner conductive layer, and a first middle conductive layer in contact with the first dielectric layer; and
the second capacitor includes a second inner conductive layer in contact with the second surface of the insulator, a second dielectric layer in contact with the second inner conductive layer, and a second middle conductive layer in contact with the second dielectric layer.

8. The circuit apparatus of claim 7 , wherein the circuit apparatus further comprises a first middle insulator on the first surface of the insulator and a second middle insulator on the second surface of the insulator, the first capacitor being embedded in the first middle insulator and the second capacitor being embedded in the second middle insulator, wherein:
the first inductor includes a first inner conductive sublayer in contact with the first middle insulator, a first insulative sublayer in contact with the first inner conductive sublayer, and a first outer conductive sublayer in contact with the first insulative sublayer; and
the second inductor includes a second inner conductive sublayer in contact with the second middle insulator, a second insulative sublayer in contact with the second inner conductive sublayer, and a second outer conductive sublayer in contact with the second insulative sublayer.

9. The circuit apparatus of claim 8 , further comprising:
one or more first vias disposed in the first middle insulator and configured to couple the first inductor to the first capacitor; and
one or more second vias disposed in the second middle insulator and configured to couple the second inductor to the second capacitor.

10. The circuit apparatus of claim 1 , wherein the at least one conductive sidewall includes one or more circuit contact surfaces, the one or more circuit contact surfaces including one or more of:
a low-frequency band contact surface that is electrically coupled to the first subset of circuit elements;
a high-frequency band contact surface that is electrically coupled to the second subset of circuit elements; and
an antenna contact surface that is configured to electrically couple one or more of the first subset of circuit elements and the second subset of circuit elements to an antenna.

11. A method of manufacturing a circuit apparatus, the method comprising:
providing an insulator having a first surface, a second surface, and a periphery;
disposing a first subset of circuit elements directly on the first surface, wherein the first subset of circuit elements includes a first inductor and a first capacitor;
disposing a second subset of circuit elements directly on the second surface, wherein the second subset of circuit elements includes a second inductor and a second capacitor; and
disposing at least one conductive sidewall on the periphery, wherein the at least one conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

12. The method of claim 11 , wherein:
the insulator includes glass; and
a thickness of the insulator is greater than a thickness of the first subset of circuit elements and greater than a thickness of the second subset of circuit elements.

13. The method of claim 11 , wherein the first subset of circuit elements are configured to filter a first frequency band and the second subset of circuit elements are configured to filter a second frequency band, the second frequency band being higher than the first frequency band.

14. The method of claim 11 , wherein the second inductor has a lower inductance than the first inductor and the second capacitor has a lower capacitance than the first capacitor.

15. The method of claim 14 , wherein:
disposing the first inductor includes patterning a first spiral pattern and plating a first spiral inductor in accordance with the first spiral pattern; and
disposing the second inductor includes patterning a second spiral pattern and plating a second spiral inductor in accordance with the second spiral pattern.

16. The method of claim 14 , further comprising:
disposing a first middle insulator on the first surface of the insulator and a second middle insulator on the second surface of the insulator, and wherein:
disposing the first inductor includes patterning and plating a first inner conductive sublayer in contact with the first middle insulator, a first insulative sublayer in contact with the first inner conductive sublayer, and a first outer conductive sublayer in contact with the first insulative sublayer; and
disposing the second inductor includes patterning and plating a second inner conductive sublayer in contact with the second middle insulator, a second insulative sublayer in contact with the second inner conductive sublayer, and a second outer conductive sublayer in contact with the second insulative sublayer.

17. The method of claim 14 , wherein:
disposing the first capacitor includes patterning and metallizing a first inner conductive layer in contact with the first surface of the insulator, applying a first dielectric

Assignees

• Qualcomm Inc

Inventors

• Yun Changhan Hobie
• Berdy David Francis
• Zuo Chengjie
• Kim Daeik Daniel
• Kim Jonghae
• Velez Mario Francisco
• Mudakatte Niranjan Sunil
• Mikulka Robert Paul

Classifications

• H01P5/12

  Coupling devices having more than two ports (H01P5/04 takes precedence) · CPC title

• H03H7/0115 Primary

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H05K3/403

  Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof (H05K3/4092 takes precedence) · CPC title

• H05K1/165

  incorporating printed inductors · CPC title

• H03H7/463

  Duplexers · CPC title