Diplexer design using through glass via technology

Patent metadata

Field	Value
Publication number	US-9203373-B2
Application number	US-201313798733-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Jan 11, 2013
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

First claim

What is claimed is:

1. A diplexer, comprising:
a substrate having a plurality of through substrate vias;
a first plurality of traces on a first outer surface of the substrate, coupled to the plurality of through substrate vias;
a second plurality of traces on a second outer surface of the substrate, opposite the first outer surface, coupled to opposite ends of the plurality of through substrate vias, the plurality of through substrate vias and traces operating as a 3D inductor; and
a layered metal-insulator-metal capacitor structure directly supported by the first outer surface of the substrate and directly coupled to the 3D inductor.

2. The diplexer of claim 1 , in which the layered metal-insulator-metal capacitor structure is supported by only one side of the substrate.

3. The diplexer of claim 1 , in which the substrate comprises glass, air, quartz, sapphire or high-resistivity silicon.

4. The diplexer of claim 1 , in which the layered metal-insulator-metal capacitor structure comprises conductive layers on opposing sides, the conductive layers having a thickness of approximately 1 um to 5 um.

5. The diplexer of claim 1 , in which the diplexer has a rejection greater than 30 dB at a frequency of 5.5 GHz.

6. The diplexer of claim 1 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

7. A diplexer, comprising:
a first port;
a second port;
a third port;
a low pass filter between two of the first port, the second port and the third port;
a second pass filter between two other of the first port, the second port and the third port, the second pass filter comprising a band pass filter or a high pass filter; and
a glass substrate supporting the first port, the second port and the third port.

8. The diplexer of claim 7 , in which the low pass filter and the second pass filter each comprise a capacitor or an inductor.

9. The diplexer of claim 8 , in which the inductor comprises a 3D inductor.

10. The diplexer of claim 8 , in which the capacitor comprises conductive layers on opposing sides, the conductive layers having a thickness of approximately 1 to 5 um.

11. The diplexer of claim 8 , in which the capacitor is supported by only one side of the substrate.

12. The diplexer of claim 7 , in which the low pass filter is a filter configured to trap frequencies from the second port, and the second pass filter is a filter configured to trap frequencies from the first port.

13. The diplexer of claim 7 , in which the second pass filter is a band pass filter, and the diplexer has a rejection greater than 30 dB at a frequency of 5.5 GHz.

14. The diplexer of claim 7 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

15. A method of fabricating a diplexer, comprising:
forming a plurality of through substrate vias in a substrate;
depositing a first plurality of traces on a first outer surface of the substrate;
depositing a second plurality of traces on a second outer surface of the substrate;
coupling the first plurality of traces to first sides of the plurality of through substrate vias;
coupling the second plurality of traces to second sides of the plurality of through substrate vias to form a serpentine 3D inductor; and
forming a layered metal-insulator-metal capacitor structure directly on the first outer surface of the substrate.

16. The method of claim 15 , further comprising integrating the diplexer into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

17. An diplexer comprising:
a substrate having a plurality of through substrate vias;
a first plurality of traces on a first outer surface of the substrate;
first means for coupling the plurality of through substrate vias on the first outer surface of the substrate;
second means for coupling opposite ends of the plurality of through substrate vias on a second outer surface of the substrate opposite the first outer surface, the first plurality of traces and the first means for coupling and the second means for coupling operating as a 3D inductor; and
means for storing charge directly supported by the first outer surface of the substrate and directly coupled to the 3D inductor.

18. The diplexer of claim 17 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

19. A method of fabricating a diplexer, comprising:
the step of forming a plurality of through substrate vias in a substrate;
the step of depositing a first plurality of traces on a first outer surface of the substrate;
the step of depositing a second plurality of traces on a second outer surface of the substrate;
the step of coupling the first plurality of traces to first sides of the plurality of through substrate vias;
the step of coupling the second plurality of traces to second sides of the plurality of through substrate vias to form a serpentine 3D inductor; and
the step of forming a layered metal-insulator-metal capacitor structure directly on the first outer surface of the substrate.

20. The method of claim 19 , further comprising the step of integrating the diplexer into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

Assignees

• Qualcomm Inc

Inventors

• Zuo Chengjie
• Kim Jonghae
• Velez Mario Francisco
• Lan Je-Hsiung
• Kim Daeik D
• Yun Changhan
• Berdy David F
• Mikulka Robert P
• Nowak Matthew M
• Zhang Xiangdong
• See Puay H

Classifications

• H10W70/692 Primary

  Ceramics or glasses · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title