Semiconductor package including a semiconductor die having redistributed pads

Patent metadata

Field	Value
Publication number	US-10103076-B2
Application number	US-201715425582-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Nov 10, 2005
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface. The method further includes forming a plurality of conductive pads over the plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes to which the respective conforming conductive pad of said plurality of conductive pads is coupled and extending over said insulation body.

First claim

What is claimed is:

1. A method for fabricating a semiconductor package, the method comprising:
coupling a first major surface of a semiconductor die to a metallic body;
depositing an insulation body over said semiconductor die;
removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface;
forming a plurality of conductive pads over said plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads is extending over said insulation body; and
forming a passivation body between each adjacent one of said plurality of conductive pads, wherein a side surface of said passivation body is partially covered by said metallic body.

2. The method of claim 1 , wherein said insulation body is photoimageable.

3. The method of claim 1 , wherein said plurality of conductive pads are formed by forming a seed layer of a conductive material on said plurality of electrodes and plating a conductive body on said seed layer.

4. The method of claim 1 , wherein said plurality of conductive pads are comprised of copper.

5. The method of claim 1 , wherein said metallic body is a metallic plate.

6. The method of claim 1 , wherein said metallic body is a metallic clip.

7. The method of claim 6 , wherein said metallic clip includes a connection surface that is generally coplanar with said plurality of conductive pads.

8. The method of claim 6 , wherein said metallic clip is cup-shaped.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Pavier Mark
• Sawle Andrew N
• Standing Martin

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title