Digital signal processing blocks with embedded arithmetic circuits

Patent metadata

Field	Value
Publication number	US-10101966-B1
Application number	US-201715478056-A
Country	US
Kind code	B1
Filing date	Apr 3, 2017
Priority date	Jan 29, 2013
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first specialized processing block comprising:
a first arithmetic operator stage configured to:
receive at least one input;
perform a first arithmetic operation on the at least one input; and
output a first result based at least in part on the first arithmetic operation;

a second arithmetic operator stage configured to:
receive the first result from the first arithmetic operator stage;
perform a second arithmetic operation on the first result; and
output a second result based at least in part on the second arithmetic operation; and

a multiplexor configured to select the at least one input from at least two inputs prior to performing the first arithmetic operation of the first arithmetic operator stage; and

a second specialized processing block disposed adjacent to the first specialized processing block, the integrated circuit comprising interconnect circuitry that routes one or more connections directly between the first specialized processing block and the second specialized processing block, wherein the second specialized processing block is configured to:
receive the second result from the second arithmetic operator stage;
perform a third arithmetic operation on the second result; and
output a third result based on the third arithmetic operation.

2. The integrated circuit of claim 1 , wherein the first specialized processing block and the second specialized processing block are configured to apply a finite impulse response (FIR) filter.

3. The integrated circuit of claim 1 , wherein the first specialized processing block comprises a register to implement a delay in the at least one input.

4. The integrated circuit of claim 3 , wherein the multiplexor is configured to receive the at least one input from the register.

5. The integrated circuit of claim 1 , wherein the second specialized processing block comprises circuitry identical to circuitry of the first specialized processing block.

6. The integrated circuit of claim 1 , wherein the second specialized processing block is configured to receive the second result from the second arithmetic operator stage via the interconnect circuitry.

7. The integrated circuit of claim 1 , wherein the second specialized processing block is configured to perform the same arithmetic operations as the first specialized processing block.

8. The integrated circuit of claim 1 , comprising register storage initialized during configuration to store constant values of finite impulse response (FIR) filter coefficients.

9. The integrated circuit of claim 1 , wherein the interconnect circuitry comprises external interconnections directly coupled between the first specialized processing block and the second specialized processing block.

10. A method, comprising:
selecting, via multiplexor circuitry, at least one input from at least two inputs;
receiving, from the multiplexor circuitry, the at least one input at a first arithmetic operator stage of a first specialized processing block;
performing a first arithmetic operation on the at least one input at the first arithmetic operator stage;
outputting a first result based on the first arithmetic operation;
receiving the first result from the first arithmetic operator stage at a second arithmetic operator stage of the first specialized processing block;
performing a second arithmetic operation on the first result at the second arithmetic operator stage; and
outputting a second result based on the second arithmetic operation to a second specialized processing block, wherein the second specialized processing block is directly connected to the first specialized processing block via interconnect circuitry.

11. The method of claim 10 , comprising applying a finite impulse response (FIR) filter using the first specialized processing block.

12. The method of claim 10 , comprising:
receiving, at the second specialized processing block, the second result from the second arithmetic operator stage;
performing, at the second specialized processing block, a third arithmetic operation on at least one input of the second specialized processing block at a third arithmetic operation stage;
outputting a third result from the third arithmetic operation stage based on the third arithmetic operation;
performing, at the second specialized processing block, a fourth arithmetic operation on the third result and the second result at a fourth arithmetic operation stage; and
outputting, at the second specialized processing block, a fourth result based on at least the fourth arithmetic operation.

13. The method of claim 10 , comprising delaying the at least one input via a register.

14. The method of claim 10 , comprising performing, at the second specialized processing block, the same arithmetic operations as the first specialized processing block.

15. A digital signal processing (DSP) system, comprising:
a first specialized processing block comprising:
a first arithmetic operator stage configured to:
receive at least one input;
perform a first arithmetic operation on the at least one input; and
output a first result based at least in part on the first arithmetic operation;

a second arithmetic operator stage configured to:
receive the first result from the first arithmetic operator stage;
perform a second arithmetic operation on the first result; and
output a second result based at least in part on the second arithmetic operation;

a multiplexor configured to select the at least one input from at least two inputs prior to performing the first arithmetic operation of the first arithmetic operator stage; and
interconnect circuitry configured to route the second result directly to a second specialized processing block disposed adjacent to the first specialized processing block.

16. The DSP system of claim 15 , wherein the first specialized processing block is configured to output at least a portion of a dot product operation.

17. The DSP system of claim 15 , comprising a register configured to delay the at least one input.

18. The DSP system of claim 15 , wherein the DSP system is integrated into a programmable logic device (PLD).

19. The DSP system of claim 15 , comprising the second specialized processing block, wherein the second specialized processing block comprises:
a third arithmetic operator stage configured to:
receive at least one other input;
perform a third arithmetic operation on the at least one other input; and
output a third result based on the third arithmetic operation; and

a fourth arithmetic operator stage configured to:
receive the third result and the second result;
perform a fourth arithmetic operation on the third result and the second result; and
output a fourth result based on the fourth arithmetic operation.

20. The DSP system of claim 15 , wherein the first specialized processing block is configured to calculate an exponent based at least in part on the at least one input.

Assignees

• Altera Corp

Inventors

• Langhammer Martin

Classifications

• G06F7/44 Primary

  Multiplying; Dividing {(G06F7/405 takes precedence)} · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06G7/14

  for addition or subtraction  (of vector quantities G06G7/22  {; computing the average by addition; differential amplifiers H03F3/45}) · CPC title

• H03H2220/04

  Pipelined · CPC title