Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10096707-B2
Application number	US-201815915105-A
Country	US
Kind code	B2
Filing date	Mar 8, 2018
Priority date	Apr 3, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
providing a substrate;
forming a first deep well region of a first conductivity type in a first portion of the substrate;
forming a second deep well region of the first conductivity type in a second portion of the substrate, the first and second deep well regions being formed with an identical doping concentration and doping depth;
forming a deep diffusion region of the first conductivity type in the substrate between the first deep well region and the second deep well region;
forming a third well region of a second conductivity type in the deep diffusion region, the third well region being a gate region of a junction field effect transistor (JFET) and configured to control a pinch off voltage of the JFET;
forming an insulation layer on a top surface of the substrate;
forming a buried impurity layer of the second conductivity type in the first and second deep well regions, the buried impurity layer being in electrical contact with the third well region;
forming a drain region in the first portion of the substrate; and
forming a source region in the second portion of the substrate, the source region and the drain region being of the first conductivity type.

2. The method of claim 1 , further comprising:
forming a pick-up region of the second conductivity type on a third portion of the substrate.

3. The method of claim 1 , further comprising:
forming a field plate on the insulation layer, the field plate being in electrical contact with the drain region to prevent a breakdown phenomenon in the semiconductor device.

4. The method of claim 1 , wherein the deep diffusion region has a graded doping profile, such that a doping concentration decreases from a first edge near the respective deep well region to a second edge away from the respective deep well region.

5. The method of claim 1 , wherein the buried impurity layer has a width that extends beyond the third well region on both sides of the third well region.

6. The method of claim 1 , wherein the deep diffusion region is spaced apart from the drain region by a first distance and is spaced apart from the source region by a second distance, and
wherein the first distance is greater than the second distance.

7. The method of claim 1 , wherein the deep diffusion region is formed through a thermal processing process that diffuses first conductive type impurities.

8. The method of claim 1 , wherein the first conductivity type is an N-type and the second conductivity type is a P-type.

9. A method for forming a semiconductor device, the method comprising:
providing a substrate;
forming a deep well region of a first conductivity type in the substrate, wherein the deep well region comprises a first deep well region of the first conductivity type in a first portion of the substrate, and a second deep well region of the first conductivity type in a second portion of the substrate;
forming a deep diffusion region of the first conductivity type in the substrate between the first deep well region and the second deep well region, the deep diffusion region having a doping concentration that is lower than that of the first and second well regions;
forming an insulation layer on a top surface of the substrate;
forming a buried impurity layer of the second conductivity type in the first and second deep well regions;
forming a drain region in the first deep well region; and
forming a source region in the second deep well region, the source region and the drain region being of the first conductivity type.

10. The method of claim 9 , wherein the first and second deep well regions have an identical doping concentration and doping depth with respect to the top surface of the substrate.

11. The method of claim 9 , wherein the second deep well region has a shallower doping depth than a doping depth of the first deep well region.

12. The method of claim 9 , further comprising:
forming a third well region of a second conductivity type contacting the deep diffusion region and a first surface of the substrate, the third well region being a gate region of a junction field effect transistor (JFET) and configured to control a pinch off voltage of the JFET.

13. The method of claim 9 , wherein the deep diffusion region is spaced apart from the drain region by a first distance and is spaced apart from the source region by a second distance, and
wherein the first distance is greater than the second distance.

14. A method for forming a semiconductor device, the method comprising:
forming a deep well region of a first conductivity type on a substrate, the deep well region comprising a diffusion region having a dopant concentration lower than that of the deep well region;
forming a junction field effect transistor (JFET) gate region of a second conductivity type on a portion of the diffusion region, the JFET gate region being configured to control a pinch-off voltage of the JFET;
forming a buried impurity layer of the second conductivity type in the deep well region, the buried impurity layer being in electrical contact with the JFET gate region;
forming a common drain region and a first source region of the first conductivity type on the deep well region; and
forming a second source region of the first conductivity type on a body region of the second conductivity type formed on the substrate.

15. The method of claim 14 , further comprising:
forming a first pick-up region of the second conductivity type on the substrate near the deep well region and a second pick-up region of the second conductivity type on the body region of the second conductivity type.

16. The method of claim 14 , further comprising:
forming a field plate on the insulation layer,
wherein the field plate is in electrical contact with the common drain region to prevent a breakdown phenomenon in the substrate.

17. The method of claim 14 , wherein the diffusion region has a graded doping profile such that a doping concentration decreases from a first edge near the deep well region to a second edge away from the deep well region.

18. The method of claim 14 , wherein the deep diffusion region is formed through a thermal processing process that diffuses first conductive type impurities.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Kim Young Bae
• Kim Kwang Il

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H01L29/66901

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L29/808

  Electricity · mapped topic