Semiconductor packages

Patent metadata

Field	Value
Publication number	US-10090278-B2
Application number	US-201615393754-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Feb 18, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate including a plurality of vias;
a chip stack on the substrate, the chip stack including a lower semiconductor chip on the substrate, an upper semiconductor chip on the lower semiconductor chip, and a middle semiconductor chip between the lower semiconductor chip and the upper semiconductor chip;
a lower non-conductive layer between the substrate and the lower semiconductor chip;
a middle non-conductive layer between the lower semiconductor chip and the middle semiconductor chip; and
an upper non-conductive layer between the middle semiconductor chip and the upper semiconductor chip, a width of the middle semiconductor chip being greater than a width of the upper semiconductor chip and less than a width of the lower semiconductor chip, wherein
the middle non-conductive layer includes a middle extension protruding outside of the middle semiconductor chip and covering side surfaces of the middle semiconductor chip, and
the middle extension has an uppermost end higher than a bottom surface of the upper semiconductor chip,
a width of the middle non-conductive layer is less than a width of the lower non-conductive layer, and
a width of the upper non-conductive layer is less than the width of the middle non-conductive layer,
the middle extension is spaced apart from the upper semiconductor chip, in plan view.

2. The semiconductor package of claim 1 , wherein
the middle semiconductor chip includes a plurality of middle semiconductor chips, and
the plurality of the middle semiconductor chips have smaller widths as a distance from a top surface of the substrate increases.

3. The semiconductor package of claim 1 , wherein
the lower non-conductive layer includes a lower extension protruding outside of the lower semiconductor chip and covering side surfaces of the lower semiconductor chip,
the upper non-conductive layer includes an upper extension protruding outside of the upper semiconductor chip and covering side surfaces of the upper semiconductor chip,
the lower extension is spaced apart from the side surfaces of the middle semiconductor chip, and
the middle extension is spaced apart from the side surfaces of the upper semiconductor chip.

4. The semiconductor package of claim 3 , wherein
the lower extension has an uppermost end higher than a bottom surface of the middle semiconductor chip.

5. The semiconductor package of claim 3 , wherein the upper extension has an uppermost end flush with or lower than a top surface of the upper semiconductor chip.

6. A semiconductor package comprising:
a plurality of non-conductive layers stacked on top of each other, each of the non-conductive layers including extension portions at respective sides that protrude upward compared to a region between the extension portions,
the non-conductive layers including an intermediate non-conductive layer between an upper non-conductive layer and a lower non-conductive layer,
a width of the intermediate non-conductive layer being less than a width of the lower non-conductive layer and greater than a width of the upper non- conductive layer;

a lower semiconductor chip between the lower non-conductive layer and the intermediate non-conductive layer such that lower semiconductor chip is on the region between the extension portions of the lower non-conductive layer;
an intermediate semiconductor chip between the intermediate non-conductive layer and the upper non-conductive layer such that intermediate semiconductor chip is on the region between the extension portions of the intermediate non-conductive layer; and
an upper semiconductor chip on the region between the extension portions of the upper non-conductive layer, a bottom surface of the upper semiconductor chip being below an uppermost end of the extension portions of the intermediate non-conductive layer, wherein
a width of the intermediate non-conductive layer is less than a width of the lower non-conductive layer, and
a width of the upper non-conductive layer is less than the width of the intermediate non-conductive layer,
the extension portions of the intermediate non-conductive layer is spaced apart from the upper semiconductor chip, in plan view.

7. The semiconductor package of claim 6 , wherein
a width of the intermediate semiconductor chip is less than a width of the lower semiconductor chip and greater than a width of the upper semiconductor chip.

8. The semiconductor package of claim 6 , wherein the lower semiconductor chip, the intermediate semiconductor chip, and the upper semiconductor chips each include a memory chip.

9. The semiconductor package of claim 6 , wherein a thickness of the intermediate semiconductor chip is less than a thickness of the upper semiconductor chip.

10. The semiconductor package of claim 6 , wherein the extension portions of the intermediate non-conductive layer are between the extension portions of the lower non-conductive layer and the extension portions of the upper non-conductive layer.

Assignees

• Park Sang Sick
• NAM Geol
• Min Tae Hong
• Hwang Jihwan
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Sick
• NAM Geol
• Min Tae Hong
• Hwang Jihwan

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title