Semiconductor device, and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10090266-B2
Application number	US-201615205414-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Aug 26, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip. The first lower insulating structure has a top surface positioned at a higher vertical level than that of the second lower insulating structure.

First claim

We claim:

1. A semiconductor device, comprising:
a semiconductor chip including:
a semiconductor chip substrate including a chip region and a boundary region, an integrated circuit being provided on the chip region;
a center pad provided on the chip region and electrically connected to the integrated circuit; a boundary pad provided on the boundary region;
a first lower insulating structure having a contact hole extending to the center pad;
a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the semiconductor chip; and
a conductive pattern comprising a contact portion, a conductive line portion, and a bonding pad portion, the contact portion filling at least part of the contact hole and the conductive line portion disposed on the first lower insulating structure to connect the contact portion to the bonding pad portion,
wherein the first lower insulating structure has a top surface positioned at a higher vertical level above the top surface of the substrate than that of the second lower insulating structure, and
wherein a first sidewall of the boundary pad is aligned with a first sidewall of the semiconductor chip substrate, such that the boundary pad is exposed to the outside of the semiconductor chip by the second lower insulating structure and the semiconductor chip substrate.

2. The semiconductor device of claim 1 , wherein:
the top surface of the first lower insulating structure is covered by the conductive pattern; and
the top surface of the second lower insulating structure does not contact any layer of the semiconductor chip.

3. The semiconductor device of claim 1 , wherein the first lower insulating structure comprises:
a first lower insulating layer adjacent to the center pad;
a second lower insulating layer on the first lower insulating layer; and
a third lower insulating layer on the second lower insulating layer, wherein the second lower insulating layer is interposed between the first and third lower insulating layers.

4. The semiconductor device of claim 3 , wherein the second lower insulating structure comprises:
a fourth lower insulating layer adjacent to the boundary pad;
a fifth lower insulating layer on the fourth lower insulating layer; and
a sixth lower insulating layer on the fifth lower insulating layer,
wherein the first and fourth lower insulating layers have top surfaces positioned at the same level,
wherein the second and fifth lower insulating layers have top surfaces positioned at the same level, and
wherein the third lower insulating layer has a top surface positioned at a higher level than that of the sixth lower insulating layer.

5. The semiconductor device of claim 3 , wherein the third lower insulating layer has a thickness greater than that of the first lower insulating layer, and
the third lower insulating layer has a thickness greater than that of the second lower insulating layer.

6. The semiconductor device of claim 3 , wherein the integrated circuit is configured to have at least one dynamic random access memory (DRAM) cell.

7. The semiconductor device of claim 1 , further comprising a barrier pattern interposed between the first lower insulating structure and the conductive pattern,
wherein the barrier pattern overlaps the conductive pattern, when viewed in a plan view.

8. The semiconductor device of claim 1 , further comprising an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip.

9. The semiconductor device of claim 1 , wherein the contact portion has a first thickness in a direction perpendicular to a top surface of the substrate and a second thickness in another direction parallel to the top surface of the substrate, and
the first thickness is greater than the second thickness.

10. The semiconductor device of claim 1 , wherein the contact portion is provided to fill at least a portion of the contact hole and to define a recess.

11. The semiconductor device of claim 8 , wherein the upper insulating structure further comprises a third opening exposing the contact portion to the outside.

12. The semiconductor device of claim 1 , wherein the center pad is electrically connected to the integrated circuit through a plurality of metal layers and a plurality of vias.

13. The semiconductor device of claim 1 , wherein, when viewed in a plan view, the center pad is provided on a center area of the chip region, and the bonding pad portion is provided on a peripheral area of the chip region.

14. The semiconductor device of claim 1 , wherein the conductive pattern is formed of an aluminum-containing material.

15. The semiconductor device of claim 1 , further comprising: a package substrate, wherein the semiconductor chip is mounted on the package substrate and is electrically connected to the package substrate through a wire; and
the semiconductor chip includes first and second surfaces opposite to each other, the first surface facing the package substrate and the second surface comprising a chip region and a boundary region enclosing the chip region,
wherein the second lower insulating structure is provided on the boundary region.

16. The semiconductor device of claim 15 , wherein the semiconductor chip is a first semiconductor chip, and further comprising:
one or more additional semiconductor chips stacked on the package substrate and the first semiconductor chip, wherein of the first semiconductor chip and the one or more additional semiconductor chips are electrically connected to the package substrate through a respective bonding pad portion and wire.

17. A semiconductor chip, comprising:
a substrate including a chip region and a boundary region horizontally separate from the chip region, an integrated circuit being provided in the chip region, and the boundary region comprising a scribe lane;
a center pad provided in the chip region and electrically connected to the integrated circuit;
a boundary pad provided in the boundary region;
a first lower insulating structure extending upward from the substrate and having a contact hole exposing the center pad;
a second lower insulating structure, extending upward from the substrate, and having a first opening exposing the boundary pad to an outside of the second lower insulating structure; and
a redistribution layer comprising a contact portion, a conductive line portion, and a bonding pad portion, the contact portion filling at least part of the contact hole and the conductive line portion disposed on the first lower insulating structure to connect the contact portion to the bonding pad portion,
wherein each of the first and second lower insulating structures has a first surface facing the substrate and a second surface opposite the first surface,
wherein the first surface of the first lower insulating structure is positioned at the same vertical level as the first surface of the second lower insulating structure, and
wherein the conductive line portion of the redistribution layer includes a bottom surface contacting the second surface of the first lower insulating structure, and positioned at a higher level than the second surface of the second lower insulating structure, such that there is a vertical gap between a height of the bottom surface of the conductive line portion contacting the second surface of the first lower insulating structure and the second surface of the second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Ae-Hee
• Kim Sang-Ki
• Jo Ahyun
• Choi Kyo-Seon

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title