Semiconductor package with interlocked connection

Patent metadata

Field	Value
Publication number	US-10090216-B2
Application number	US-201715442084-A
Country	US
Kind code	B2
Filing date	Feb 24, 2017
Priority date	Jul 11, 2013
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a support substrate having opposing first and second main surfaces and sides extending between the first and second main surfaces;
a semiconductor die attached to the first main surface of the support substrate;
an electrically conductive lead separate and spaced apart from the support substrate, and
an encapsulation material at least partly covering the support substrate, the semiconductor die and the electrically conductive lead, the encapsulation material comprising a bottom side that is coplanar with the second main surface of the support substrate and a top side that is vertically spaced apart from the bottom side,
wherein the support substrate comprises a first protrusion extending outward from a side of the support substrate, the first protrusion forming an interlocked connection with the encapsulation material, and terminating in the encapsulation material,
wherein the first protrusion comprises a narrower portion and a wider portion, the narrower portion being arranged closer to the support substrate than the wider portion,
wherein the first protrusion has a completely curved perimeter,
wherein the electrically conductive lead has a first part covered by the encapsulation material and a second part uncovered by the encapsulation material.

2. The semiconductor package of claim 1 , wherein the interlocked connection between the first protrusion and the encapsulation material is a dovetail joint with the first protrusion forming a tenon of the dovetail joint and a region of the encapsulation material adjacent the first protrusion forming a mortise of the dovetail joint.

3. The semiconductor package of claim 1 , wherein a first side of the first protrusion has a negative slope with respect to the side of the support substrate from which the first protrusion extends, and wherein a second side of the first protrusion has a positive slope with respect to the side of the support substrate from which the first protrusion extends.

4. The semiconductor package of claim 1 , wherein the first protrusion extends outward from the side of the support substrate in the same plane as the support substrate.

5. The semiconductor package of claim 1 , wherein the support substrate is a metal block and the first protrusion is a single continuous part of the metal block.

6. The semiconductor package of claim 1 , further comprising a plurality of spaced apart protrusions extending outward from a side of the support substrate and terminating in the encapsulation material, the plurality of protrusions forming the interlocked connection with the encapsulation material.

Assignees

• Infineon Technologies Ag

Inventors

• Meyer-Berg Georg
• Pufall Reinhard
• Goroll Michael
• Dudek Rainer

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title