Semiconductor module with interlocked connection

Patent metadata

Field	Value
Publication number	US-9627305-B2
Application number	US-201313939248-A
Country	US
Kind code	B2
Filing date	Jul 11, 2013
Priority date	Jul 11, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces;
a semiconductor die attached to the first main surface of the support substrate;
an electrically conductive lead separate spaced apart from the support substrate;
an encapsulation material at least partly covering the support substrate, the semiconductor die and the electrically conductive lead, the encapsulation material comprising a bottom side that is coplanar with the second main surface of the support substrate and a top side that is vertically spaced apart from the bottom side;
a first protrusion extending outward from the support substrate, forming an interlocked connection with the encapsulation material, and terminating in the encapsulation material, wherein the first protrusion comprises a narrower portion and a wider portion, the narrower portion being arranged closer to the support substrate than the wider portion; and
a second protrusion extending outward from the electrically conductive lead and being vertically offset from the bottom and top sides of the encapsulation material, the second protrusion forming an interlocked connection with the encapsulation material,
wherein the electrically conductive lead has a first part covered by the encapsulation material and a second part uncovered by the encapsulation material,
wherein the second protrusion extends from the first part of the electrically conductive lead,
wherein the first protrusion comprises a completely curved perimeter.

2. The semiconductor package of claim 1 , wherein the second protrusion extends outward from the electrically conductive lead in the same plane as the electrically conductive lead.

3. The semiconductor package of claim 1 , wherein the interlocked connection between the first protrusion and the encapsulation material is a dovetail joint with the first protrusion forming a tenon of the dovetail joint and a region of the encapsulation material adjacent the first protrusion forming a mortise of the dovetail joint.

Assignees

• Infineon Technologies Ag

Inventors

• Meyer-Berg Georg
• Pufall Reinhard
• Goroll Michael
• Dudek Rainer

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title