Method for producing a conductor line

Patent metadata

Field	Value
Publication number	US-10090192-B2
Application number	US-201514936339-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Apr 20, 2012
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

First claim

What is claimed is:

1. A method for producing a conductor line of a semiconductor component, the method comprising:
providing a partially completed semiconductor component with a bottom side and a top side spaced distant from the bottom side in a vertical direction;
providing an etchant;
arranging a dielectric layer that is doped with a dopant on the top side by subsequently depositing a number of sub-layers, wherein a dopant concentration of the dopant has a maximum in a first one of the sub-layers, and wherein the dopant concentration of the dopant is
zero in a second one of the sub-layers and greater than zero in a third one of the sub-layers, wherein the first one of the sub-layers is located between the second one of the sub-layers and the third one of the sub-layers;
forming a trench in each of the sub-layers of the dielectric layer using an anisotropic plasma etch process;
widening the trench by etching the trench with the etchant at different etch rates caused by different concentrations of the dopant; and
forming a conductor line by filling the widened trench with an electrically conductive material.

2. The method as claimed in claim 1 , wherein each of the sub-layers comprises, in the vertical direction, a thickness of at least 100 nm.

3. The method as claimed in claim 1 , wherein each of the sub-layers comprises, in the vertical direction, a thickness of at least 400 nm.

4. The method as claimed in claim 1 , wherein the number of sub-layers is at least 5.

5. The method as claimed in claim 1 , wherein the dopant comprises, within the dielectric layer and along a line parallel to the vertical direction, a maximum dopant concentration; and a place of the maximum dopant concentration is spaced distant from the top side.

6. The method as claimed in claim 1 , wherein the dopant is one of phosphorus (P), boron (B), silver (Ag), arsenic (As), and argon (Ar).

7. The method as claimed in claim 1 , further comprising:
arranging a mask layer on the top side, the mask layer comprising an opening; and
forming the trench by etching the dielectric layer underneath the opening, thereby using the mask layer as an etching mask.

8. The method as claimed in claim 7 , wherein filling the widened trench comprises introducing the electrically conductive material through the opening into the widened trench.

9. The method as claimed in claim 7 , further comprising removing partially or completely the mask layer and a part of the electrically conductive material arranged in the opening.

10. The method as claimed in claim 7 , wherein, in a cross-sectional plane perpendicular to a running direction of the widened trench,
the opening comprises a minimum width; and
the widened trench comprises, in a region between the opening and the bottom side, a maximum width, wherein the maximum width is greater than the minimum width.

11. The method as claimed in claim 10 , wherein, in the cross-sectional plane perpendicular to the running direction of the widened trench, the maximum width is greater than a difference between
a distance between the bottom side and the opening; and
a distance between the bottom side and the conductor line.

12. The method as claimed in claim 7 , wherein no additional material is deposited on a surface of the widened trench, prior to filling the widened trench with the electrically conductive material.

13. The method as claimed in claim 1 , wherein the dielectric layer comprises a silicon oxide (SiOx).

14. The method as claimed in claim 1 , wherein the conductor line comprises, in a cross-sectional plane perpendicular to a running direction of the widened trench, a surface with a surface location at which a radius of curvature of the location is in a range from 0.4 μm to 3.2 μm.

15. The method as claimed in claim 1 , wherein the conductor line comprises, in a cross-sectional plane perpendicular to a running direction of the widened trench, a continuous surface path that extends, in the vertical direction, over a distance of at least 100 nm or of at least 0.8 μm and that has everywhere a radius of curvature in a range from 0.4 μm 3.2 μm.

16. The method as claimed in claim 1 , wherein the electrically conductive material
(a) consists of copper or aluminum; or
(b) comprises copper or aluminum; or
(c) consists of copper and aluminum; or
(d) comprises copper and aluminum; or
(e) comprises or consists of polycrystalline semiconductor material.

17. The method as claimed in claim 1 , wherein the conductor line is an outer winding of a coil of a coreless transformer of the semiconductor component.

18. The method as claimed in claim 17 , wherein the coreless transformer galvanically decouples a control circuit configured to control a semiconductor element from a control electrode of the semiconductor element.

19. The method as claimed in claim 1 , wherein the conductor line is an electrode of a capacitor.

20. The method as claimed in claim 19 , wherein the capacitor galvanically decouples a control circuit configured to control a semiconductor element from a control electrode of the semiconductor element.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Stecher Matthias
• Menath Markus
• Zankl Andreas
• Reitmeier Anja

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title