Open block management

Patent metadata

Field	Value
Publication number	US-10089170-B1
Application number	US-201615183710-A
Country	US
Kind code	B1
Filing date	Jun 15, 2016
Priority date	Jun 15, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Systems and methods are disclosed for open block management. In certain embodiments, an apparatus may comprise a circuit configured to determine an error sensitivity of a last-written page of a block of a solid state memory that is in an open state where the block has not been fully filled with data. The error sensitivity may include a value that represents a susceptibility to developing data errors while in the open state. The circuit may perform a first error mitigation procedure when the error sensitivity is lower than a first threshold, include increasing an open block timeout period applied to the last-written page. The circuit may perform a second error mitigation procedure when the error sensitivity is higher than the first threshold, including copying data from the block to a new location when a first open block timeout is reached.

First claim

What is claimed is:

1. An apparatus comprising:
a circuit configured to:
determine an error sensitivity of a last-written page of a block of a solid state memory that is in an open state where the block has not been fully filled with data, the error sensitivity including a value that represents a susceptibility to developing data errors while in the open state;
perform a first error mitigation procedure when the error sensitivity is lower than a first threshold; and
perform a second error mitigation procedure when the error sensitivity is higher than the first threshold, the second error mitigation procedure includes:
reading data from the block when a first open block timeout is reached, the first open block timeout including a duration of time the last-written page is allowed to remain in an open state before data of the block is refreshed; and
copying the data to a new storage location of the solid state memory.

2. The apparatus of claim 1 further comprising:
the first error mitigation procedure includes increasing an open block timeout period applied to the last-written page.

3. The apparatus of claim 2 further comprising:
increasing the open block timeout period includes:
determining whether the error sensitivity of the last-written page is lower than a second threshold; and
applying a second open block timeout longer than the first open block timeout when the error sensitivity is not lower than the second threshold.

4. The apparatus of claim 3 further comprising:
increasing the open block timeout period further includes not applying the open block timeout when the error sensitivity is lower than the second threshold, including not refreshing data from the block based on the block remaining in the open state.

5. The apparatus of claim 4 comprising the circuit further configured to:
determine error sensitivity metrics for the last-written page based on errors encountered when reading data from the last-written page;
increase a value of the error sensitivity when the error sensitivity metrics are higher than a first sensitivity adjustment threshold; and
decrease the value of the error sensitivity when the error sensitivity metrics are lower than a second sensitivity adjustment threshold.

6. The apparatus of claim 5 comprising the circuit further configured to:
determine error sensitivity of a plurality of most-recently written pages, including the last-written page, the plurality of most-recently written pages being less than all pages in the block; and
determine which of the first error mitigation procedure and the second error mitigation procedure to perform based on comparing the error sensitivity of the plurality of most-recently written pages to the first threshold.

7. A method comprising:
determining an error sensitivity of a last-written page of a block of a solid state memory that is in an open state where the block has not been fully filled with data, the error sensitivity including a value that represents a susceptibility to developing data errors while in the open state;
performing reliability enhancing operations to prevent data loss based on the error sensitivity of the last-written page, including:
performing a first error mitigation procedure when the error sensitivity is lower than a first threshold, the first error mitigation procedure includes increasing an open block timeout period applied to the last-written page, the open block timeout period including a duration of time the last-written page is allowed to remain in an open state before data of the block is refreshed; and
performing a second error mitigation procedure when the error sensitivity is higher than the first threshold.

8. The method of claim 7 further comprising:
the second error mitigation procedure includes:
reading data from the block when the first open block timeout period is reached; and
copying the data to a new storage location of the solid state memory.

9. The method of claim 7 further comprising:
increasing the open block timeout period includes:
determining whether the error sensitivity of the last-written page is lower than a second threshold; and
applying a second open block timeout longer than the first open block timeout when the error sensitivity is not lower than the second threshold.

10. The method of claim 7 further comprising:
increasing the open block timeout period includes:
determining whether the error sensitivity of the last-written page is lower than a second threshold; and
not applying the open block timeout when the error sensitivity is lower than the second threshold, including not refreshing data from the block based on the block remaining in the open state.

11. The method of claim 7 further comprising:
determining error sensitivity metrics for the last-written page based on errors encountered when reading data from the last-written page;
increasing a value of the error sensitivity when the error sensitivity metrics are higher than a first sensitivity adjustment threshold; and
decreasing the value of the error sensitivity when the error sensitivity metrics are lower than a second sensitivity adjustment threshold.

12. The method of claim 7 further comprising:
determining error sensitivity of a plurality of most-recently written pages, including the last-written page, the plurality of most-recently written pages being less than all pages in the block; and
performing one of the first error mitigation procedure and the second error mitigation procedure based on comparing the error sensitivity of the plurality of most-recently written pages to the first threshold.

13. An apparatus comprising:
a solid state memory configured to store data to a plurality of blocks, each block including a plurality of pages;
a circuit configured to:
determine an error sensitivity of a last-written page of a block of the solid state memory that is in an open state where the block has not been fully filled with data, the error sensitivity including a value that represents a susceptibility to developing data errors while in the open state;
perform a first error mitigation procedure when the error sensitivity is lower than a first threshold; and
perform a second error mitigation procedure when the error sensitivity is higher than the first threshold.

14. The apparatus of claim 13 further comprising:
the second error mitigation procedure includes:
reading data from the block when a first open block timeout is reached, the first open block timeout including a duration of time the last-written page can is allowed to remain in an open state before data of the block is refreshed; and
copying the data to a new storage location of the solid state memory.

15. The apparatus of claim 13 further comprising:
the first error mitigation procedure includes increasing an open block timeout period applied to the last-written page, the open block timeout period including a duration of time the last-written page is allowed to remain in an open state before data of the block is refreshed.

16. The apparatus of claim 15 further comprising:
increasing the open block timeout period includes:
determining whether the error sensitivity of the last-written page is lower than a second threshold;
applying a second open block timeout longer than the first open block timeout when the error sensitivity is not lower than the second threshold; and
not applying the open block timeout when the error sensitivity is lower than the second threshold, including not refreshing data from the block based on the block remaining in the open state.

Assignees

• Seagate Technology Llc

Inventors

• Goss Ryan James
• Khoueir Antoine
• Patapoutian Ara

Classifications

• G06F11/0754

  by exceeding limits · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title