Printed circuit board with flux reservoir

US10085338B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10085338-B2
Application numberUS-201514863591-A
CountryUS
Kind codeB2
Filing dateSep 24, 2015
Priority dateSep 24, 2015
Publication dateSep 25, 2018
Grant dateSep 25, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Method and apparatus for establishing an electrical interconnection between an electrical lead and a printed circuit board (PCB), such as a PCB used in a data storage device. In some embodiments, the PCB includes a multi-layer substrate having at least one conductive layer and at least one electrically insulative layer. An electrically conductive pad is provided on a facing surface of the substrate in electrical communication with the at least one conductive layer. A flux reservoir is placed adjacent the pad which extends from the facing surface into the substrate. A solder mask layer is provided on the facing surface of the base structure which surrounds the pad and extends into the reservoir. The solder mask layer and reservoir collect liquid flux from a soldering operation used to form a solder joint between the pad and a conductive lead of an electronic component.

First claim

Opening claim text (preview).

What is claimed is: 1. A printed circuit board (PCB) comprising: a multi-layer substrate having at least one conductive layer and at least one electrically insulative layer; an electrically conductive pad on a facing surface of the substrate in electrical communication with the at least one conductive layer, the pad having a side surface extending in a direction away from the facing surface and a top surface nominally parallel to the substrate and disposed a selected distance from the facing surface; a flux reservoir adjacent the pad which extends from the facing surface into the substrate; and a solder mask layer on the facing surface of the substrate which surrounds the pad in contacting relation to the side surface of the pad and which extends into the reservoir, the solder mask layer having a top surface aligned with the top surface of the pad and disposed at the selected distance from the facing surface, the solder mask layer and reservoir configured to collect liquid flux responsive to a soldering operation used to form a solder joint between the pad and a conductive lead of an electronic component, the flux reservoir characterized as a non-plated-through hole (NPTH) having a sidewall and a bottom surface, the sidewall and the bottom surface of the NPTH coated by the solder mask layer, and the solder mask layer having a first width adjacent the pad, a second width adjacent the flux reservoir, and a narrow neck portion having a third width less than the first and second widths between the pad and the flux reservoir. 2. The PCB of claim 1 , wherein the PCB is a rigid PCB. 3. The PCB of claim 1 , wherein the PCB is a flexible PCB. 4. The PCB of claim 1 , wherein the solder mask layer is sloped in a direction toward the flux reservoir. 5. The PCB of claim 1 , characterized as a PCB of a data storage device. 6. The PCB of claim 1 , in combination with the electrical component attached thereto by way of the solder joint attaching the conductive lead to the pad. 7. A printed circuit board assembly (PCBA), comprising: a printed circuit board (PCB) characterized as a multi-layer substrate comprising a conductive layer, an electrically insulative layer, an electrically conductive pad on a facing surface of the substrate in electrical communication with the conductive layer, a flux reservoir adjacent the pad which extends from the facing surface into the substrate, and a solder mask layer on the facing surface of the substrate which surrounds the pad and extends into the reservoir, the electrically conductive pad having a top surface nominally parallel to the facing surface and a side surface nominally perpendicular to the facing surface, the solder mask layer contactingly abutting the side surface of the pad and having a top layer aligned with the top layer of the pad; an electrical component having a conductive lead supported by the PCB; and a solder joint which attaches the electrical component to the pad, the flux reservoir containing a volume of flux resulting from the formation of the solder joint, the flux reservoir characterized as a non-plated-through hole (NPTH) having a sidewall and a bottom surface, the sidewall and the bottom surface of the NPTH coated by the solder mask layer, and the solder mask layer having a first width adjacent the pad, a second width adjacent the flux reservoir, and a narrow neck portion having a third width less than the first and second widths between the pad and the flux reservoir. 8. The PCBA of claim 7 , wherein the solder mask layer is sloped in a direction toward the flux reservoir. 9. The PCBA of claim 7 , wherein the solder comprises a metal alloy and a flux, the metal alloy comprising at least a selected one of tin (Sn), lead (Pb), copper (Cu), silver (Ag), bismuth (Bi), indium (In), zinc (Zn), gold (Au) or antimony (Sb), the flux comprising at least a selected one of a resin, an amine compound, an epoxy, a carboxyl group compound, or an acid.

Assignees

Inventors

Classifications

  • Application of solder · CPC title

  • Pads for surface mounting, e.g. lay-out · CPC title

  • Pb as the principal constituent · CPC title

  • Au as the principal constituent · CPC title

  • Bi as the principal constituent · CPC title

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Frequently asked questions

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What does patent US10085338B2 cover?
Method and apparatus for establishing an electrical interconnection between an electrical lead and a printed circuit board (PCB), such as a PCB used in a data storage device. In some embodiments, the PCB includes a multi-layer substrate having at least one conductive layer and at least one electrically insulative layer. An electrically conductive pad is provided on a facing surface of the subst…
Who is the assignee on this patent?
Seagate Technology Llc
What technology area does this patent fall under?
Primary CPC classification H05K3/3452. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).