Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-9853003-B1
Application number	US-201715480573-A
Country	US
Kind code	B1
Filing date	Apr 6, 2017
Priority date	Jul 26, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip,
wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and
the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

2. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a plurality of first coil pattern layers, and
a coil pattern included in each of the plurality of coil pattern layers forms a coil of which a central axis independently corresponds to a stacking direction of the plurality of first coil pattern layers.

3. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a plurality of first coil pattern layers, and
a coil pattern included in each of the plurality of coil pattern layers is electrically connected to each other through a via formed in the first connection member to form a coil of which a central axis corresponds to a stacking direction of the plurality of first coil pattern layers.

4. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a plurality of first coil pattern layers,
a plurality of coil patterns included in each of the plurality of coil pattern layers are electrically connected to each other through a plurality of vias formed in the first connection member to form a coil of which a central axis corresponds to a direction perpendicular to a stacking direction of the plurality of first coil pattern layers.

5. The fan-out semiconductor package of claim 4 , wherein the coil includes a plurality of outer layers composed of layers of the plurality of first coil pattern layers, disposed on an uppermost layer and a lowermost layer, based on the stacking direction, and a plurality of inner layers composed of layers of the plurality of first coil pattern layers, disposed between the plurality of outer layers,
the coil has a spiral path rotating while alternately passing through the plurality of outer layers and the plurality of inner layers based on the central axis.

6. The fan-out semiconductor package of claim 1 , wherein the second connection member includes a second coil pattern layer electrically connected to a connection pad of the semiconductor chip, and
a coil pattern included in each of the first coil pattern layer and the second coil pattern layer is electrically connected to each other to form a coil.

7. The fan-out semiconductor package of claim 6 , wherein the first connection member includes a plurality of first coil pattern layers,
the second connection member includes at least one second coil pattern layer, and
a plurality of coil patterns included in each of the plurality of first coil pattern layers and a plurality of coil patterns included in each of the at least one second coil pattern layer are electrically connected to each other through a plurality of vias formed in the first connection member and the second connection member to form a coil of which a central axis corresponds to a direction perpendicular to a stacking direction of the plurality of first coil pattern layers and the at least one second coil pattern layer.

8. The fan-out semiconductor package of claim 7 , wherein the coil includes a plurality of outer layers composed of layers of the plurality of first coil pattern layers and the at least one second coil pattern layer, disposed on an uppermost layer and a lowermost layer, based on the stacking direction, and a plurality of inner layers composed of layers of the plurality of first coil pattern layers and the at least one second coil pattern layer, disposed between the plurality of outer layers, and
the coil has a spiral path rotating while alternately passing through the plurality of outer layers and the plurality of inner layers based on the central axis.

9. The fan-out semiconductor package of claim 8 , wherein, in at least one layer between the plurality of inner layers, a coil pattern is not formed therein.

10. The fan-out semiconductor package of claim 9 , wherein, in the at least one layer in which a coil pattern is not formed, a magnetic layer is formed therein.

11. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first region through a fourth region surrounding the semiconductor chip, and
the first coil pattern layer is formed in a single region of the first region through the fourth region.

12. The fan-out semiconductor package of claim 1 , wherein the semiconductor chip includes an application processor (AP) and a power management integrated circuit (PMIC),
the first coil pattern layer forms a power inductor (PI), and
one end and the other end of the PI are electrically connected to the AP and the PMIC, respectively.

13. The fan-out semiconductor package of claim 9 , wherein a lower surface of the first redistribution layer is disposed on a level higher than a lower surface of the connection pad.

14. The fan-out semiconductor package of claim 9 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

15. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

16. The fan-out semiconductor package of claim 15 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer.

17. The fan-out semiconductor package of claim 15 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

18. The fan-out semiconductor package of claim 15 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second connection member.

19. The fan-out semiconductor package of claim 15 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

20. The fan-out semiconductor package of claim 15 , wherein a lower surface of the third redistribution layer is disposed on a level below a lower surface of the connection pad.

Assignees

• Samsung Electro Mech

Inventors

• Han Mi Ja
• Choi Seong Hee
• Kim Han
• Kim Moon Il
• Park Dae Hyun

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title