Defect marking for semiconductor wafer inspection

Patent metadata

Field	Value
Publication number	US-10082470-B2
Application number	US-201715430817-A
Country	US
Kind code	B2
Filing date	Feb 13, 2017
Priority date	Sep 27, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Methods and systems for accurately locating buried defects previously detected by an inspection system are described herein. A physical mark is made on the surface of a wafer near a buried defect detected by an inspection system. In addition, the inspection system accurately measures the distance between the detected defect and the physical mark in at least two dimensions. The wafer, an indication of the nominal location of the mark, and an indication of the distance between the detected defect and the mark are transferred to a material removal tool. The material removal tool (e.g., a focused ion beam (FIB) machining tool) removes material from the surface of the wafer above the buried defect until the buried defect is made visible to an electron-beam based measurement system. The electron-beam based measurement system is subsequently employed to further analyze the defect.

First claim

What is claimed is:

1. A defect locating system comprising:
a marking tool configured to physically mark a surface of a wafer at one or more locations near a defect buried in a vertically stacked semiconductor structure fabricated on the wafer; and
an optical inspection tool comprising:
an illumination source configured to generate an amount of illumination light;
an illumination subsystem configured to focus the amount of illumination light at a vertically stacked semiconductor structure disposed on a wafer;
a collection subsystem configured to collect light from the vertically stacked structure in response to the focused illumination light;
a detector configured to detect the light collected and generate one or more output signals indicative of the amount of collected light; and
a computing system configured to:
receive the one or more output signals;
determine a location of the buried defect based on the one or more output signals;
determine the locations of the one or more physical marks based on the one or more output signals; and
determine a distance between the location of the buried defect and the locations of the one or more physical marks in at least two dimensions parallel to the surface of the wafer.

2. The defect locating system of claim 1 , further comprising:
a material removal tool configured to remove material from the surface of the wafer; and
a computing system configured to:
receive an indication of the locations of the one or more physical marks and the distance between the location of the buried defect and the locations of the one or more physical marks; and
communicate a command signal to the material removal tool that causes the material removal tool to remove material from the wafer at the location of the buried defect; and

a defect verification tool configured to image the buried defect after removal of the material.

3. The defect locating system of claim 2 , wherein the material removal tool is a focused ion beam machining tool.

4. The defect locating system of claim 1 , wherein the marking tool and the optical inspection tool are integrated into a single wafer processing tool.

5. The defect locating system of claim 1 , wherein the marking tool includes any of a laser, a mechanical scribe, and an electron beam.

6. The defect locating system of claim 1 , wherein the surface of the wafer is physically marked at two or more locations near the buried defect.

7. The defect locating system of claim 1 , wherein each of the one or more physical marks are located within five micrometers of the location of the buried defect.

8. The defect locating system of claim 1 , wherein the distance between the location of the buried defect and the locations of the one or more physical marks is determined with a precision of less than one hundred nanometers.

9. The defect locating system of claim 1 , wherein the buried defect is located at least fifty nanometers below the surface of the wafer.

10. The defect locating system of claim 1 , wherein the vertically stacked semiconductor structure is a three dimensional NAND memory device.

11. The defect locating system of claim 1 , wherein the illumination source of the optical inspection system is a broadband laser sustained plasma light source.

12. A method comprising:
physically marking a surface of a wafer at one or more locations near a defect buried in a vertically stacked semiconductor structure fabricated on the wafer with a marking tool;
focusing an amount of illumination light generated by an illumination source of an optical inspection tool onto the vertically stacked semiconductor structure disposed on the wafer;
collecting light from the vertically stacked structure in response to the focused illumination light with a collection subsystem of the optical inspection tool;
detecting the light collected and generating one or more output signals indicative of the amount of collected light with a detector of the optical inspection tool;
determining a location of the buried defect based on the one or more output signals;
determining the locations of the one or more physical marks based on the one or more output signals; and
determining a distance between the location of the buried defect and the locations of the one or more physical marks in at least two dimensions parallel to the surface of the wafer, wherein the determining of the location of the buried defect, the determining of the locations of the one or more physical marks, and the determining of the distance are performed by a computing system.

13. The method of claim 12 , further comprising:
removing material from the surface of the wafer at the location of the buried defect based at least in part on the distance between the location of the buried defect and the locations of the one or more physical marks.

14. The method of claim 13 , further comprising:
imaging the buried defect with an defect verification tool after removal of the material.

15. The method of claim 12 , wherein the marking of the surface of the wafer involves any of a laser, a mechanical scribe, and an electron beam.

16. The method of claim 12 , wherein the surface of the wafer is physically marked at two or more locations near the buried defect.

17. The method of claim 12 , wherein each of the one or more physical marks are located within five micrometers of the location of the buried defect.

18. The method of claim 12 , wherein the distance between the location of the buried defect and the locations of the one or more physical marks is determined with a precision of less than one hundred nanometers.

19. The method of claim 12 , wherein the vertically stacked semiconductor structure is at least three micrometers thick and the buried defect is located at least fifty nanometers below the surface of the wafer.

20. A defect locating system comprising:
a marking tool configured to physically mark a surface of a wafer at one or more locations near a defect buried in a vertically stacked semiconductor structure fabricated on the wafer; and
an optical inspection tool comprising:
an illumination source configured to generate an amount of illumination light;
an illumination subsystem configured to focus the amount of illumination light at a vertically stacked semiconductor structure disposed on a wafer;
a collection subsystem configured to collect light from the vertically stacked structure in response to the focused illumination light;
a detector configured to detect the light collected and generate one or more output signals indicative of the amount of collected light; and
a computing system comprising:
one or more processors; and
a non-transitory, computer-readable medium storing instructions, that when executed by the one or more processors, cause the defect locating system to:
receive the one or more output signals;
determine a location of the buried defect based on the one or more output signals;
determine the locations of the one or more physical marks based on the one or more output signals; and
determine a distance between the location of the buried defect and the locations of the one or more physical marks in at least two dimensions parallel to the surface of the wafer.

21. The defect locating system of claim 20 , further comprising:
a material removal tool configured to remove material from the surface of the wafer, the non-transitory, computer-readable medium further storing instructions, that when executed by the one or more processors, cause the defect

Assignees

• Kla Tencor Corp

Inventors

• Shortt David
• Lange Steven
• Wei Junwei
• Kapp Daniel
• Amsden Charles

Classifications

• G01N1/44

  Sample treatment involving radiation, e.g. heat · CPC title

• G01N21/8851 Primary

  Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges (G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002) · CPC title

• G01N2021/888

  Marking defects · CPC title

• G01N21/9501

  Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20) · CPC title

• G01N21/8806

  Specially adapted optical and illumination features · CPC title