Robust high speed sensor interface for remote sensors

Patent metadata

Field	Value
Publication number	US-10079650-B2
Application number	US-201514959226-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Dec 4, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Systems, methods, and apparatuses are discussed that enable robust, high-speed communication of sensor data. One example system includes a sensor bus, an electronic control unit (ECU), and one or more sensors. The ECU is coupleable to the sensor bus and configured to generate a synchronization signal, and is configured to output the synchronization signal to the sensor bus. The one or more sensors are also coupleable to the sensor bus, and at least one sensor of the one or more sensors is configured to sample sensor data in response to the synchronization signal and to output the sampled sensor data to the sensor bus.

First claim

What is claimed is:

1. A system, comprising:
a sensor bus;
an electronic control unit (ECU) coupleable to the sensor bus and configured to generate a synchronization signal, wherein the ECU is configured to output the synchronization signal to the sensor bus; and
one or more sensors coupleable to the sensor bus, wherein at least one sensor of the one or more sensors is configured to acquire respective sensor data in response to the synchronization signal and to output the a digital representation of the acquired sensor data in a respective frame to the sensor bus with a respective predetermined latency relative to an acquisition of the respective sensor data, the frame comprising a synchronization bit and at least one resynchronization bit, the at least one resynchronization bit being transmitted between a first data block of the frame and a second data block of the frame, wherein, when the one or more sensors is two or more sensors, each sensor of the two or more sensors other than a first sensor of the two or more sensors is configured to output the respective frame of that sensor immediately after the respective frame of another sensor of the two or more sensors.

2. The system of claim 1 , wherein the at least one sensor of the one or more sensors is associated with one or more addresses of a plurality of addresses, and wherein the synchronization signal comprises an address element that indicates the at least one sensor via indicating a selected address of the one or more addresses.

3. The system of claim 2 , wherein the synchronization signal comprises the synchronization bit followed by the address element.

4. The system of claim 2 , wherein the acquired sensor data is output via a data frame having a constant length, wherein the synchronization signal has the constant length.

5. The system of claim 2 , wherein the selected address of the plurality of addresses is associated with at least two selected sensors of the one or more sensors, wherein the selected sensors are configured to acquire the sensor data simultaneously in response to the synchronization signal, and further configured to transmit their respective digital representation of the acquired sensor data at different points in time, wherein a first sensor of the at least two selected sensors transmits the digital representation of the acquired sensor data to the sensor bus with the predetermined latency, and wherein a remaining sensor of the at least two selected sensors transmits the digital representation of the acquired sensor data to the sensor bus with a second latency relative to the acquisition, the second latency being different from the predetermined latency.

6. The system of claim 1 , wherein the at least one sensor is further configured to transmit the digital representation of the acquired sensor data in response to the synchronization signal.

7. The system of claim 1 , wherein the synchronization signal and the outputted digital representation of the acquired sensor data are coded via a non-return-to-zero (NRZ) coding scheme.

8. The system of claim 1 , wherein the at least one sensor is configured to output the digital representation of the acquired sensor data via one or more data frames, wherein each data frame comprises one or more data bits and an associated resynchronization bit of the at least one resynchronization bit.

9. The system of claim 8 , wherein the one or more data frames comprise a plurality of data frames, wherein each of the plurality of data frames have the same length.

10. The system of claim 8 , wherein the one or more data frames comprise a plurality of data frames, wherein at least two of the plurality of data frames have different lengths.

11. The system of claim 8 , wherein each of the one or more data frames comprises the associated resynchronization bit followed by the plurality of data bits.

12. The system of claim 1 , wherein the synchronization signal is a broadcast synchronization signal, wherein the at least one sensor comprises the one or more sensors, wherein the one or more sensors are configured to acquire the sensor data simultaneously in response to the synchronization signal, and further configured to transmit their respective digital representation of the acquired sensor data at different points in time.

13. The system of claim 1 , wherein the sensor bus comprises a differential interface, and wherein each of the one or more sensors are coupleable to the sensor bus via a differential transceiver.

14. A sensor, comprising:
a differential transceiver coupleable to a sensor bus, wherein the differential transceiver is configured to receive a synchronization signal; and
a sensor element configured to acquire sensor data in response to the synchronization signal,
wherein the differential transceiver is further configured to transmit a digital representation of the acquired sensor data in a frame to the sensor bus with a predetermined latency relative to an acquisition of the sensor data, the frame comprising a synchronization bit and at least one resynchronization bit, the at least one resynchronization bit being transmitted between a first data block of the frame and a second data block of the frame.

15. The sensor of claim 14 , wherein the differential transceiver is configured to transmit and to receive via a non-return-to-zero (NRZ) code.

16. The sensor of claim 14 , wherein the differential transceiver is further configured to transmit the digital representation of the acquired sensor data to the sensor bus in response to the synchronization signal.

17. The sensor of claim 14 , wherein the sensor is associated with at one or more addresses of a plurality of addresses, wherein the synchronization signal comprises an address element, the address element indicating the sensor module being addressed by the synchronization signal via the address element comprising one of the associated one or more addresses.

18. A system, comprising:
means for communication;
means for controlling coupleable to the means for communication and configured to generate a synchronization signal, wherein the means for controlling is configured to output the synchronization signal to the means for communication; and
one or more means for sensing coupled to the means for communication, wherein at least one means for sensing is configured to acquire sensor data in response to the synchronization signal and to output a digital representation of the acquired sensor data in a respective frame to the means for communication with a respective predefined latency relative to an acquisition of the sensor data, the frame comprising a synchronization bit and at least one resynchronization bit, the at least one resynchronization bit being transmitted between a first data block of the frame and a second data block of the frame,

wherein, when the one or more means for sensing is two or more means for sensing, each means for sensing of the two or more means for sensing other than a first means for sensing of the two or more means for sensing is configured to output the respective frame of that means for sensing immediately after the respective frame of another means for sensing of the two or more means for sensing.

19. The system of claim 18 , wherein the at least one means for sensing is associated with at least one address of a plurality of addresses, and wherein the synchronization signal indicates the at least one means for sensing via indicating an address of the plurality of addresses.

20. The system of claim 19 , wherein the synchroniza

Assignees

• Infineon Technologies Ag

Inventors

• Aichriedler Leo

Classifications

• H04L7/044

  using a single bit, e.g. start stop bit · CPC title

• H04J3/0652

  Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] (bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035) · CPC title

• H04J3/0638 Primary

  Clock or time synchronisation among nodes; Internode synchronisation (synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43) · CPC title

• H04Q9/04

  Arrangements for synchronous operation · CPC title

• H04L2012/40273

  the transportation system being a vehicle · CPC title