Method and system for single-line inter-integrated circuit (I2C) bus

Patent metadata

Field	Value
Publication number	US-9569386-B2
Application number	US-201313863565-A
Country	US
Kind code	B2
Filing date	Apr 16, 2013
Priority date	Apr 16, 2013
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Embodiments of a system and method are disclosed. One embodiment is an I2C compatible device. The I2C compatible device includes an SDA interface for connection to an SDA line and a single-line I2C module configured to transmit a sync word from the SDA interface over the SDA line and following the sync word, to transmit I2C data from the SDA interface over the SDA line such that digital data is communicated via a single line. In an embodiment, the sync word is a sync byte+NACK.

First claim

What is claimed is:

1. An inter-integrated circuit (I2C) compatible device comprising:
a serial data line (SDA) interface for connection to an SDA line of a bus;
a single-line I2C module configured to:
transmit a sync word from the SDA interface over the SDA line of the bus, wherein the sync word is a SYNC BYTE+Not Acknowledge (NACK) bit; and
following transmission of the sync word, transmit I2C data from the SDA interface over the SDA line of the bus such that digital data is communicated over the bus via a single line, wherein the next byte that is transmitted from the SDA interface over the SDA line of the bus following the sync word is a 7 bit slave address plus a data direction bit formatted according to the I2C specification, wherein the data direction bit indicates either a write operation or a read operation.

2. The I2C compatible device of claim 1 , wherein the I2C compatible device is a master I2C device.

3. The I2C compatible device of claim 1 , wherein the sync word is a 010101011 bit stream with the SDA line initially held high.

4. The I2C compatible device of claim 1 , wherein the single-line I2C module is configured to transmit the sync word and the I2C data according to a time synchronization protocol.

5. The I2C compatible device of claim 1 , wherein the single-line I2C module is configured to transmit the sync word and the I2C data according to an edge synchronization protocol.

6. An inter-integrated circuit (I2C) compatible device comprising:
an SDA interface for connection to an SDA line of a bus;
a single-line I2C module configured to:
recognize a sync word in digital data received at the SDA interface via the SDA line of the bus, wherein the sync word is a SYNC BYTE+Not Acknowledge (NACK) bit; and
upon recognizing the sync word, decode the received digital data as I2C data, wherein the next byte that is received at the SDA interface via the SDA line of the bus following the sync word is decoded as a 7 bit slave address plus a data direction bit formatted according to the I2C specification, wherein the data direction bit indicates either a write operation or a read operation.

7. The I2C compatible device of claim 6 , wherein the I2C compatible device is a slave I2C device.

8. The I2C compatible device of claim 6 , wherein the sync word is a 010101011 bit stream with the SDA line initially held high.

9. The I2C compatible device of claim 6 , wherein the single-line I2C module is configured to decode the sync word and the I2C data according to a time synchronization protocol.

10. The I2C compatible device of claim 6 , wherein the single-line I2C module is configured to decode the sync word and the I2C data according to an edge synchronization protocol.

11. The I2C compatible device of claim 6 wherein the I2C compatible device is backwards compatible with the two-line I2C specification, which uses both SDA and serial clock line (SCL) lines.

12. A method for communicating digital data between a master and a slave over a single line of a bus, the method comprising:
transmitting a sync word over the single line of the bus, wherein the sync word is a SYNC BYTE+Not Acknowledge (NACK) bit;
following transmission of the sync word, transmitting I2C data over the single line of the bus, wherein the next byte that is transmitted over the single line of the bus following the sync word is a 7 bit slave address plus a data direction bit formatted according to the I2C specification, wherein the data direction bit indicates either a write operation or a read operation.

13. The method of claim 12 further comprising, receiving the sync word, recognizing the sync word, and decoding the I2C data upon recognizing the sync word, wherein the next byte that is received via the single line of the bus following the sync word is decoded as a 7 bit slave address plus a data direction bit formatted according to the I2C specification, wherein the data direction bit indicates either a write operation or a read operation.

14. The method of claim 12 wherein the sync word and I2C data are transmitted according to a time synchronization protocol.

15. The method of claim 12 wherein the sync word and I2C data are transmitted according to an edge synchronization protocol.

Assignees

• Nxp Bv

Inventors

• Du David Alan

Classifications

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title