Heterogenous memory access

Patent metadata

Field	Value
Publication number	US-9513692-B2
Application number	US-201314030515-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Sep 18, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.

First claim

What is claimed is:

1. A method for accessing memory comprising:
partitioning memory into a plurality of areas, each area defined by attributes, the areas being TSV (Through Silicon Via) areas accessible from stacked die arrangements;
characterizing data according to an expected usage of the data; and
selecting an area of the plurality of areas in which to store the data based on the expected usage of the data, each area of the partitioned memory remaining addressable from a memory controller in the same manner without regard to the memory area in which the data is stored.

2. The method of claim 1 wherein the expected usage of the data is based on at least one of frequency of access of the data, expediency in retrieval of the data, and longevity of the data.

3. The method of claim 1 wherein the data is storable and retrievable from any of the plurality of areas without explicit identification of the area from which the retrieval is performed.

4. The method of claim 1 further comprising dynamically modifying the attributes of the area in response to the expected usage.

5. The method of claim 4 further comprising:
identifying an access period and a retention period of area of memory; and
modifying a voltage attribute of the area such that the voltage level is modified according to the expected usage based on the needs of power consumption and speed.

6. The method of claim 5 further comprising modifying a voltage attribute of the area such that the voltage is lower during the retention period for maintaining the data and the voltage is higher during the access period for fast retrieval of the data.

7. The method of claim 1 further comprising identifying an operating mode, the operating mode indicative of a priority of the attributes such that areas exhibiting a higher priority attribute are favored; and
mapping the data based on the priority of attributes, such that areas exhibiting attributes corresponding to the high priority are favored and areas exhibiting attributes corresponding to a lower priority are employed less frequently.

8. A method for accessing memory comprising:
partitioning memory into a plurality of areas, each area defined by attributes;
characterizing data according to an expected usage of the data; and
selecting an area of the plurality of areas in which to store the data based on the expected usage of the data, wherein an operating mode prioritizes the plurality of areas for usage based on the attributes, the operating modes including:
a performance mode, the performance mode favoring memory areas having a fast retrieval;
an efficiency mode favoring memory areas having low power consumption with an acceptable retrieval time; and
a resilience mode favoring memory areas having high retention times for maintaining operation with minimal power and thermal stress while maintaining responsiveness.

9. The method of claim 8 wherein selecting includes mapping between the attributes and the expected usage wherein:
a performance attribute identifies the speed with which the data is recalled from an area of memory, and is employed for data frequently accessed in timing sensitive computations
a retention attribute identifies the duration which the data will remain in the area of memory without a power refresh, and is employed for data infrequently accessed in latency tolerant computations; and
an efficiency attribute indicates a power consumption for maintaining the data in the area of memory, and is employed when heat or battery considerations limit memory access.

10. The method of claim 7 further comprising receiving operating statistics from the plurality of memory areas, wherein the attributes are based on the received operating statistics.

11. The method of claim 10 wherein the operating statistics include temperature, statistic counters and timeout counters.

12. The method of claim 7 wherein the mapping further comprises invoking a heuristic for:
receiving sensor feedback on a temperature of frequently accessed areas, and
redirecting memory usage to less frequently used areas based on the received sensor feedback.

13. The method of claim 7 wherein the mapping further comprises invoking a heuristic for:
maintaining counters for accesses to areas; and
redirecting memory usage from areas having a high access count to areas having a lower count of access.

14. The method of claim 7 wherein the mapping further comprises invoking a heuristic for:
receiving timer input corresponding to data retention times;
identifying data approaching a limit if retention time for the area in which it resides; and
redirecting memory usage to areas having higher retention times based on the received timer input.

15. The method of claim 1 wherein the areas TSV (Through Silicon Via) areas are accessible from bus accessible banks.

16. A memory controller comprising:
a memory subdivided into a plurality of memory areas, each area defined by attributes;
heuristic logic operable to characterize data according to an expected usage of the data; and
a memory access medium for mapping the data to an area of the plurality of areas based on correlation of the expected usage with the attributes of the area, each area of the partitioned memory remaining addressable from a memory controller in the same manner without regard to the memory area in which the data is stored, the memory access medium configured to:
Identify, based on memory sensor input, an area of memory exhibiting a need for power correction; and
modify the attributes of the area for reducing power consumption and heat generation in response to the identified high temperature; and

a display for rendering the mapped data.

17. The controller of claim 16 wherein the expected usage of the data is based on at least one of frequency of access of the data, expediency in retrieval of the data, and longevity of the data.

18. The controller of claim 16 wherein each area of the partitioned memory remains addressable from a memory controller in the same manner without regard to the memory area in which the data is stored.

19. The controller of claim 16 wherein the memory areas are configured for dynamic modification of the attributes in response to the expected usage.

20. The controller of claim 16 wherein the heuristic defines an operating mode, the operating mode indicative of a priority of the attributes such that areas exhibiting a higher priority attribute are favored; and
the memory access medium is responsive to the heuristic logic for mapping the data based on the priority of attributes, such that areas exhibiting attributes corresponding to the high priority are favored and areas exhibiting attributes corresponding to a lower priority are employed less frequently.

21. The controller of claim 16 wherein the heuristic logic includes operating modes for prioritizing the areas based on the attributes, the operating modes including:
a performance mode, the performance mode favoring memory areas having a fast retrieval;
an efficiency mode favoring areas having low power consumption with an acceptable retrieval time; and
a resilience mode favoring areas having high retention times for maintaining operation with minimal power and thermal stress while maintaining responsiveness.

22. The controller of claim 16 wherein the heuristic is configured to map between the attributes and the expected usage is performed wherein:
the performance attribute identifies the speed with which the data i

Assignees

• Saraswat Ruchir
• Gries Matthias
• Cowley Nicholas P
• Intel Corp

Inventors

• Saraswat Ruchir
• Gries Matthias
• Cowley Nicholas P

Classifications

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title