High resistivity SOI wafers and a method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10079170-B2
Application number	US-201415112083-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Jan 23, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA- nitrides, semiconductor oxides, and any combination thereof.

First claim

What is claimed is:

1. A multilayer handle structure comprising:
a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate comprises a p-type dopant and has a bulk resistivity between about 750 ohm cm and about 100,000 Ohm-cm;
an intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate, wherein the intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprising a material selected from the group consisting of Si 1-x Ge x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , and any combination thereof wherein x, y, and z are molar ratios with values between 0.1 and 0.9, and further wherein the molar ratio of Ge in the intermediate semiconductor layer increases in the direction perpendicular from the single crystal silicon wafer handle substrate and toward a semiconductor oxide layer;
a charge trapping layer in interfacial contact with the intermediate semiconductor layer; and
a semiconductor oxide layer in interfacial contact with the charge trapping layer, wherein the charge trapping layer is between the intermediate semiconductor layer and the semiconductor oxide layer.

2. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 750 ohm cm and about 10,000 Ohm-cm.

3. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 750 ohm cm and about 5,000 Ohm-cm.

4. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

5. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

6. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

7. The multilayer handle structure of claim 1 wherein the single crystal silicon wafer handle substrate further comprises a dielectric layer in interfacial contact with the front surface thereof, and further wherein the dielectric layer is in interfacial contact with the intermediate semiconductor layer.

8. The multilayer handle structure of claim 7 wherein the dielectric layer comprises silicon dioxide.

9. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer comprises a strained intermediate semiconductor layer.

10. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer comprises a partially relaxed intermediate semiconductor layer.

11. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer comprises a fully relaxed intermediate semiconductor layer.

12. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer has a thickness of between about 1 nanometer and about 2000 nanometers.

13. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer has a thickness of between about 10 nanometers and about 2000 nanometers.

14. multilayer handle structure of claim 1 wherein the intermediate semiconductor layer has a thickness of between about 20 nanometers and about 1000 nanometers.

15. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , wherein x, y, and z are molar ratios with values between 0.2 and 0.7.

16. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge x , wherein the value of x is between 0.1 and 0.9.

17. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge, wherein the value of x is between 0.2 and 0.7.

18. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge x and further wherein the molar ratio of Ge in the intermediate semiconductor layer increases in the direction perpendicular from the single crystal silicon wafer handle substrate and toward the semiconductor oxide layer.

19. The multilayer handle structure of claim 18 , wherein the value of x is between 0.1 and 0.9.

20. The multilayer handle structure of claim 18 , wherein the value of x is between 0.2 and 0.7.

21. The multilayer handle structure of claim 1 wherein the charge trapping layer comprises polycrystalline silicon.

22. The multilayer handle structure of claim 1 further comprising a first charge trapping layer between the intermediate semiconductor layer and the semiconductor oxide layer and a second charge trapping layer between the intermediate semiconductor layer and the single crystal semiconductor handle substrate.

23. The multilayer structure of claim 1 wherein the intermediate semiconductor layer further comprises implanted boron.

24. The multilayer structure of claim 1 wherein the intermediate semiconductor layer further comprises implanted argon.

25. The multilayer handle structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises a material selected from the group consisting of Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , wherein x, y, and z are molar ratios with values between 0.1 and 0.9.

26. A multilayer handle structure comprising:
a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate comprises a p-type dopant and has a minimum bulk resistivi

Assignees

• Sunedison Semiconductor Ltd
• Globalwafers Co Ltd

Inventors

• Peidous Igor
• Kommu Srikanth
• Wang Gang
• Thomas Shawn George

Classifications

• H10P90/1918

  including charge trapping layers, e.g. polycrystalline materials · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H01L21/76254

  Electricity · mapped topic