Electronic package with antenna structure

US10074621B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10074621-B2
Application numberUS-201615181489-A
CountryUS
Kind codeB2
Filing dateJun 14, 2016
Priority dateMar 28, 2016
Publication dateSep 11, 2018
Grant dateSep 11, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic package, comprising: a carrier; at least one electronic component disposed on the carrier; at least one antenna structure disposed on the carrier and consisting of a plurality of spacing members and at least one wire, wherein the wire connects any two adjacent ones of the spacing members, and each of the spacing members has at least one conductive pad connected with the wire; and an encapsulating layer formed on the carrier and encapsulating the electronic component and a portion of the antenna structure, wherein at least one of the spacing members is exposed from the encapsulating layer. 2. The electronic package of claim 1 , wherein the electronic component is electrically connected with the carrier. 3. The electronic package of claim 1 , wherein one of the spacing members is disposed on the carrier. 4. The electronic package of claim 1 , wherein one of the spacing members is electrically connected with the electronic component through another wire. 5. The electronic package of claim 1 , wherein one of the spacing members includes at least one conductive pillar electrically connected with the carrier. 6. The electronic package of claim 1 , wherein one of the spacing members is electrically connected with the carrier through another wire. 7. The electronic package of claim 1 , further comprising a passive element disposed on the carrier. 8. The electronic package of claim 7 , wherein the passive element is electrically connected with one of the spacing members through another wire. 9. The electronic package of claim 7 , wherein the passive element is electrically connected with the electronic component through another wire. 10. The electronic package of claim 1 , wherein one of the spacing members is disposed on the electronic component.

Assignees

Inventors

Classifications

  • H01Q1/243Primary

    with built-in antennas · CPC title

  • between a chip and a laterally-adjacent discrete passive device · CPC title

  • between a chip and a stacked discrete passive device · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10074621B2 cover?
Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.
Who is the assignee on this patent?
Siliconware Precision Industries Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01Q1/243. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).