Memory reliability using error-correcting code

Patent metadata

Field	Value
Publication number	US-9772901-B2
Application number	US-201514707471-A
Country	US
Kind code	B2
Filing date	May 8, 2015
Priority date	May 8, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A method and system are provided for error correction in a memory. Error correction code (ECC) for data stored in a portion of the memory is enabled. A location and number of errors for the portion of the memory is then stored. It is determined if the number of errors exceeds a predetermined number of errors. If the number of errors exceeds the predetermined number, then the data stored in the portion of the memory is refreshed. If refreshing does not correct the errors, then a different ECC may be used.

First claim

What is claimed is:

1. A method for error correction in a memory, the method comprising:
enabling error correction code (ECC) for data stored in a portion of the memory to determine a location and number of the errors within the portion of the memory, wherein the portion of the memory is part of a block of the memory;
storing the location and the number of errors for the portion of the memory;
determining that the number of errors in the portion of the memory exceeds a predetermined number of errors for the portion of the memory;
refreshing the portion of the memory to correct errors in the portion of the memory in response to the number of errors in the portion of memory exceeding the predetermined number of errors for the portion of the memory;
determining that a number of errors in the block of the memory exceeds a predetermined number of errors for the block of the memory in response to determining that the refreshing the portion of the memory did not correct the errors in the data; and
storing the data in a different block of the memory in response to determining that the number of errors in the block of the memory exceeds the predetermined number of errors for the block of the memory.

2. The method of claim 1 , further comprising:
determining that the refreshing the portion of the memory did not correct the errors in the data; and
marking the portion of the memory as uncorrectable in response to the refreshing the portion of the memo did not correct the errors in the data.

3. The method of claim 1 , wherein storing a location and number of errors further comprises storing the location and number of errors in a cache memory.

4. The method of claim 3 , wherein the cache is a multi-way cache.

5. The method of claim 1 , further comprising:
determining that refreshing the portion of the memory did not correct the errors in the data; and
enabling a different ECC for the portion of the memory to correct the errors in the portion of the memory in response to the refreshing the portion of the memory did not correct the errors in the data.

6. The method of claim 5 , further comprising:
determining that enabling a different ECC did not correct the errors in the data; and
storing the data in a different portion of the memory in response to determining that the different ECC did not correct the errors in the data.

7. The method of claim 5 , wherein the ECC is for correcting one-bit errors, and wherein the different ECC is expanded to correct two-bit errors.

8. The method of claim 1 , wherein the memory is characterized as being a non-volatile memory.

9. A method for error correction in a memory, the method comprising:
enabling error correction code (ECC) for data stored in a portion of the memory to determine a location and number of the errors within the portion of the memory, wherein the portion of the memory is part of a block of the memory;
storing the location and the number of errors detected by the ECC for the portion of the memory;
determining that the number of errors in the portion of the memory exceeds a predetermined number of errors for the portion of the memory;
enabling a different ECC for the portion of the memory to correct errors in the portion of the memo in response to the number of errors in the portion of the memory exceeding the predetermined number of errors for the portion of the memory;
determining that a number of errors in the block of the memory exceeds a predetermined number of errors for the block of the memory in response to determining that the different ECC did not correct the errors in the data; and
storing the data in a different block of the memory in response to determining that the number of errors in the block of the memory exceeds the predetermined number of errors for the block of the memory.

10. The method of claim 9 , further comprising:
determining that enabling a different ECC did not correct the errors in the data; and
marking the portion of the memory as uncorrectable in response to determining that the different ECC did not correct the errors in the data.

11. The method of claim 9 , further comprising:
determining that enabling a different ECC did not correct the errors in the data; and
refreshing the portion of the memory to correct the errors in the portion of the memory in response to determining that the different ECC did not correct the errors in the data.

12. The method of claim 11 , further comprising:
refreshing the portion of the memory to correct errors in the portion of the memory in response to the number of errors exceeding the predetermined number of errors;
determining that refreshing the portion of the memory did not correct the errors in the data; and
marking the portion of the memory as uncorrectable in response to the refreshing the portion of the memory did not correct the errors in the data.

13. The method of claim 9 , wherein the ECC is for correcting one-bit errors, and wherein the different ECC is expanded to correct two-bit errors.

14. The method of claim 9 , wherein the memory is characterized as being a multi-level cell (MLC) flash memory.

15. The memory of claim 9 , wherein storing a location and number of errors further comprises storing the location and number of errors in a cache memory.

16. A system, comprising:
a bus for communicating information;
a non-volatile memory coupled to the bus;
an error correction code (ECC) block coupled to the bus, the ECC block for executing ECC on the information stored in the non-volatile memory to determine a number of errors and locations of the errors in the non-volatile memory;
a system memory coupled to the bus, the system memory for storing the number of errors detected by the ECC, and for storing the locations of the errors; and
a program/erase block for the non-volatile memory, the program/erase block for performing a refresh operation of a stored location of the non-volatile memory to correct errors in the stored location of the non-volatile memory in response to the number of errors exceeding a limit, wherein the stored location is part of a block of the non-volatile memory, the program/erase block to determine that a number of errors in the block of the non-volatile memory exceeds a predetermined number of errors for the block of the non-volatile memory in response to a determination that the refresh operation did not correct the errors in the data, and to store the data in a different block of the non-volatile memory in response to determining that the number of errors in the block of the non-volatile memory exceeds the predetermined number of errors for the block of the non-volatile memory.

17. The system of claim 16 , wherein the ECC block further comprises executing a different ECC on the information stored in the non-volatile memory if the refresh operation did not correct the errors.

18. The system of claim 17 , wherein the information is stored in a different location of the non-volatile memory if after the different ECC is executed the number of errors exceeds the limit.

19. The system of claim 16 , wherein the non-volatile memory is characterized as being a multi-level cell (MLC) flash memory.

20. The system of claim 16 , wherein the system memory is characterized as being a multi-way associative cache.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Hoekstra George P
• Ramaraju Ravindraraj

Classifications

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F11/0766

  Error or fault reporting or storing · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title