Non-volatile memory with multi-pass programming

Patent metadata

Field	Value
Publication number	US-10068656-B2
Application number	US-201615391006-A
Country	US
Kind code	B2
Filing date	Dec 27, 2016
Priority date	Dec 27, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

First claim

What is claimed is:

1. A non-volatile memory apparatus, comprising:
a plurality of non-volatile memory cells arranged in groups of memory cells;
a plurality of word lines connected to the memory cells, each word line is connected to multiple groups of memory cells, each of the groups of memory cells is connected to multiple word lines of the plurality of word lines; and
one or more control circuits connected to the memory cells and the word lines, the one or more control circuits are configured to separately program the groups of memory cells using a multi-pass programming process including performing programming of memory cells that are directly connected to two directly adjacent word lines and are part of a first group of memory cells followed by performing programming of memory cells that are directly connected to the two directly adjacent word lines and are part of a second group of memory cells such that the one or more control circuits are configured to complete the multi-pass programming process for all memory cells directly connected to one of the two directly adjacent word lines before starting the multi-pass programming process for memory cells directly connected to another word line.

2. The non-volatile memory apparatus of claim 1 , wherein:
each group of memory cells comprises multiple units of serially connected memory cells;
each unit of serially connected memory cells connects to all of the word lines of the plurality of word lines;
each group of memory cells connects to all of the word lines of the plurality of word lines; and
each group of memory cells is mutually exclusive of other groups of memory cells.

3. The non-volatile memory apparatus of claim 2 , wherein:
the programming for memory cells that are directly connected to two directly adjacent word lines and are part of the first group of memory cells comprises sequentially performing a first pass of a multi-pass programming process and a last pass of the multi-pass programming process.

4. The non-volatile memory apparatus of claim 1 , wherein:
the programming for memory cells that are directly connected to two directly adjacent word lines and are part of the first group of memory cells and the programming for memory cells that are directly connected to the two directly adjacent word lines and are part of the second group of memory cells are part of a multi-pass programming process.

5. The non-volatile memory apparatus of claim 4 , wherein:
the one or more control circuits are configured to perform the multi-pass programming process by, after the completing the multi-pass programming process for the memory cells directly connected to a first word line and in a first group, starting the multi-pass programming process for memory cells directly connected to a second word line and in a second group.

6. The non-volatile memory apparatus of claim 4 , wherein:
the one or more control circuits are configured to start the multi-pass programming for memory cells connected to a particular word line and in a particular group subsequent to completing the multi-pass programming for memory cells connected to an adjacent word line and in an adjacent group, the adjacent word line is next to the particular word line.

7. The non-volatile memory apparatus of claim 4 , wherein:
the one or more control circuits are configured to perform the multi-pass programming process for the memory cells by starting programming for memory cells connected to a particular word line and in a particular group and then completing programming for memory cells connected to an adjacent word line and in the particular group prior to starting programming for memory cells connected to the particular word line and a next group.

8. The non-volatile memory apparatus of claim 1 , further comprising:
a plurality of select lines connected to the memory cells and the one or more control circuits, the select lines are configured to select the groups of memory cells, the non-volatile memory cells are arranged in NAND strings, the NAND strings are divided into groups of NAND strings, each group of the NAND strings comprises one of the groups of the memory cells.

9. The non-volatile memory apparatus of claim 1 , wherein:
the one or more control circuits are configured to perform programming for memory cells that are directly connected to two directly adjacent word lines and are part of the first group of memory cells by programming memory cells directly connected to a first word line and are part of the first group of memory cells and subsequently programming memory cells directly connected to a second word line and are part of the first group of memory cells; and
the one or more control circuits are configured to perform programming for memory cells that are directly connected to the two directly adjacent word lines and are part of a second group of memory cells by programming memory cells directly connected to the first word line and are part of the second group of memory cells and subsequently programming memory cells directly connected to the second word line and are part of the second group of memory cells.

10. The non-volatile memory apparatus of claim 1 , wherein:
the programming for memory cells that are directly connected to two directly adjacent word lines and are part of the first group of memory cells does not program the memory cells that are directly connected to the two adjacent word lines and are part of the second group of memory cells; and
the programming for memory cells that are directly connected to the two directly adjacent word lines and are part of the second group of memory cells does not program the memory cells that are directly connected to the two adjacent word lines and are part of the first group of memory cells.

11. The non-volatile memory apparatus of claim 1 , wherein:
memory cells directly connected to a common word line and in a same group of memory cells comprise a unit of programming; and
the memory cells that are directly connected to the two directly adjacent word lines and are part of the first group of memory cells and the memory cells that are directly connected to the two directly adjacent word lines and are part of the second group of memory cells are in a same block.

12. The non-volatile memory apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are arranged in a three dimensional monolithic memory structure.

13. A method of programming non-volatile memory, comprising:
performing a first pass of a multi-pass programming process for memory cells directly connected to a first word line and in a first unit of programming for the first word line;
performing the first pass of the multi-pass programming process for memory cells directly connected to a second word line and in a first unit of programming for the second word line, the second word line is directly adjacent to the first word line;
after the performing the first pass of the multi-pass programming process for the memory cells directly connected to the first word line and in the first unit of programming for the first word line and before the performing the first pass of the multi-pass programming process for the memory cells directly connected to the second word line and in the first unit of programming for the second word line, performing a last pass that completes the multi-pass programming process for the memory cells directly connected to a third word line and in the first unit of programming for the third word line;
after the performing the first pass of the multi-pass programming process for the memory cells directly connected to the second word line and in the first unit of programming

Assignees

• Sandisk Technologies Llc

Inventors

• Dutta Deepanshu
• Puthenthermadam Sarath
• Yip Chris

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title