Programming memory with reduced short-term charge loss

Patent metadata

Field	Value
Publication number	US-9230663-B1
Application number	US-201414472872-A
Country	US
Kind code	B1
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.

First claim

What is claimed is:

1. A method for programming in a memory device, comprising:
performing rough programming of a set of memory cells to threshold voltages comprising threshold voltages which are below final verify voltages of different target data states, the memory cells are connected to a word line, the set of memory cells comprises memory cells of one target data state of the different target data states and memory cells of another target data state of the different target data states, the final verify voltages of the different target data states comprise one final verify voltage of the one target data state and another final verify voltage of the another target data state, and the another final verify voltage is greater than the one final verify voltage;
after the rough programming, applying at least one negative voltage to the word line; and
after the applying the at least one negative voltage to the word line, performing additional programming of the set of memory cells to threshold voltages which are above the final verify voltages of the different target data states.

2. The method of claim 1 , wherein:
the performing the rough programming of the set of memory cells comprises applying a single program pulse on the word line while enabling programming of the memory cells of the one target data state and while inhibiting programming of the memory cells of the another target data state, without performing a verify test for the memory cells of the one target data state.

3. The method of claim 2 , wherein:
the performing the rough programming of the set of memory cells comprises applying another single program pulse on the word line while enabling programming of the memory cells of the another target data state and while inhibiting programming of the memory cells of the one target data state, without performing a verify test for the memory cells of the another target data state; and
the another single program pulse has an amplitude which is higher than an amplitude of the single programming pulse.

4. The method of claim 2 , wherein:
the additional programming comprises incremental step pulse programming for each target data state of the different target data states.

5. The method of claim 1 , wherein:
the performing the rough programming of the memory cells comprises performing incremental step pulse programming for the memory cells of the one target data state.

6. The method of claim 5 , wherein:
the performing the rough programming of the memory cells comprises detecting a completion of the rough programming for the memory cells of the one target data state; and
in response to the detecting, applying a single program pulse on the word line while enabling programming of the memory cells of the another target data state and inhibiting programming of the memory cells of the one target data state, without performing a verify test for the memory cells of the another target data state.

7. The method of claim 5 , wherein the performing incremental step pulse programming for the memory cells of the one target data state comprises applying program pulses to the word line while enabling programming of the memory cells of the one target data state, the method further comprising:
determining a number of the program pulses which are used when at least a specified number of the memory cells of the one target data state pass a verify test; and
determining an initial program voltage for the additional programming based on the number, wherein the additional programming comprises incremental step pulse programming, and the initial program voltage is relatively lower when the number is relatively lower.

8. The method of claim 5 , further comprising:
detecting a programming speed of the memory cells of the one target data state during the incremental step pulse programming for the memory cells of the one target data state; and
determining an initial program voltage for the additional programming based on the programming speed, wherein the additional programming comprises incremental step pulse programming and the initial program voltage is relatively lower when the programming speed is relatively faster.

9. The method of claim 5 , further comprising:
initiating programming of the memory cells of the another target data state when the memory cells of the one target data state reach a programming milestone during the incremental step pulse programming.

10. The method of claim 1 , further comprising:
for each memory cell of the set of memory cells, biasing a drain of the memory cell during the applying of the at least one negative voltage to the word line to cause the memory cell to have a negative gate-to-drain voltage.

11. The method of claim 10 , wherein:
the drains of the memory cells of the one target data state and the drains of the memory cells of the another target data state are biased via respective bit lines.

12. The method of claim 1 , wherein:
the applying the at least one negative voltage to the word line comprises:
applying one negative voltage to the word line while biasing drains of the memory cells of the one target data state and drains of the memory cells of the another target data state so that the memory cells of the one target data state have a gate-to-drain voltage which is higher in magnitude than a magnitude of a gate-to-drain voltage of the memory cells of the another target data state; and
applying another negative voltage to the word line while biasing the drains of the memory cells of the one target data state and the drains of the memory cells of the another target data state so that the gate-to-drain voltage of the memory cells of the another target data state is higher in magnitude than the magnitude of the gate-to-drain voltage of the memory cells of the one target data state.

13. The method of claim 12 , wherein:
a magnitude of the another negative voltage is higher than a magnitude of the one negative voltage.

14. A memory device, comprising:
a set of memory cells connected to a word line, the set of memory cells comprises memory cells with different target data states; and
a control circuit, the control circuit is configured to:
perform rough programming of the set of memory cells, the rough programming does not use a verify test for at least some of the memory cells,
after the rough programming, apply at least one negative voltage to the word line, and
after the at least one negative voltage is applied to the word line, perform additional programming of the set of memory cells, the additional programming uses a verify test for each memory cell in the set of memory cells.

15. The memory device of claim 14 , wherein the rough programming uses a verify test for a lowest target data state of the different target data states, the method further comprising;
determining a programming speed of memory cells of the lowest target data state during the rough programming; and
determining an initial program voltage for the additional programming based on the programming speed, where the initial program voltage is relatively lower when the programming speed is relatively faster.

16. The memory device of claim 15 , wherein:
the rough programming does not use a verify test for higher target data states of the different target data states.

17. The memory device of claim 14 , wherein:
the set of memory cells comprises charge-trapping memory cells.

18. The memory device of claim 14 , wherein:
the set of memory cells is in a three-dimensional stacked memory structure comprising alternating conductive layers

Assignees

• Sandisk Technologies Inc

Inventors

• Lu Ching-Huang
• Dong Yingda
• Pang Liang
• Kuo Tien-Chien

Classifications

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title