Multiple pass programming for memory with different program pulse widths

Patent metadata

Field	Value
Publication number	US-9324419-B2
Application number	US-201414331784-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Jul 15, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. After completion of a full programming pass, a verify test is performed to identify cells for which reprogramming is warranted. The reprogramming can include multiple program-verify iterations which use longer program pulses than in the full programming pass. Moreover, the number of program-verify iterations is limited to reduce the reprogramming time. In one approach, cells of all target data states are programmed together. In another approach, cells of different target data states are programmed separately.

First claim

What is claimed is:

1. A method for programming in a memory device, comprising:
performing a plurality of program-verify iterations in one programming pass for a set of memory cells until a completion criterion is met for the one programming pass, wherein the set of memory cells comprises respective subsets of memory cells, each respective subset of memory cells has a respective target data state defined by a respective verify voltage and the completion criterion is met when at least a specified percentage of memory cells of each set of memory cells has a threshold voltage which is above the respective verify voltage;
after the completion criterion is met for the one programming pass, identifying memory cells of each respective target data state for which reprogramming is warranted by performing a verify test to identify memory cells of each respective target data state having a threshold voltage which exceeded and then fell below a respective verify voltage; and
performing a plurality of program-verify iterations in a reprogramming pass for the memory cells of each respective target data state for which reprogramming is warranted, wherein for each respective target data state, a width of a program pulse applied to the set of memory cells during the program-verify iterations in the reprogramming pass is longer than a width of a program pulse applied to the set of memory cells during the program-verify iterations in the one programming pass.

2. The method of claim 1 , wherein:
for each respective subset of memory cells, a respective verify voltage of the respective target data state in the reprogramming pass is higher than the respective verify voltage of the respective target data state in the one programming pass.

3. The method of claim 1 , wherein:
the plurality of program-verify iterations in the reprogramming pass comprise a separate set of program-verify iterations for each respective target data state;
the widths of the program pulse applied to the set of memory cells during the program-verify iterations in the reprogramming pass comprise a different width for each of the separate sets of program verify iterations; and
the different widths are greater for relatively higher target data states among the respective target data states than for relatively lower target data states among the respective target data states.

4. The method of claim 3 , wherein:
for each separate set of program-verify iterations and for each respective target data state, the width of the program pulse applied to the set of memory cells is based on number of memory cells for which reprogramming is warranted.

5. The method of claim 3 , wherein:
for each separate set of program-verify iterations and for each respective target data state, the width of the program pulse applied to the set of memory cells is based on a programming speed in the one programming pass.

6. The method of claim 3 , wherein:
for at least one of the separate sets of program-verify iterations, the width of the program pulse applied to the set of memory cells is based on a programming speed in another of the separate sets of program-verify iterations.

7. The method of claim 3 , wherein:
each of the separate sets of program-verify iterations comprises no more than a maximum allowable number of program-verify iterations; and
at least one of the memory cells for which reprogramming is warranted and which does not pass a verify test in one of the sets of program-verify iterations is allowed to be programmed by one additional program pulse, without verify, of a program-verify iteration of another of the sets of program-verify iterations.

8. The method of claim 3 , wherein:
each of the separate sets of program verify iterations uses a different staircase progression of program pulses; and
the different staircase progressions of program pulses have different step sizes.

9. The method of claim 3 , wherein:
each of the separate sets of program verify iterations uses a different staircase progression of program pulses; and
at least one of the different staircase progressions of program pulses has an initial magnitude which is not consistent with a staircase progression of program voltages of a prior one of the different staircase progressions of program voltages.

10. The method of claim 1 , wherein:
the plurality of program-verify iterations in the reprogramming pass are common to each respective target data state.

11. The method of claim 10 , wherein:
the width of the program pulse applied to the set of memory cells is based on a programming speed of the set of memory cells in the one programming pass.

12. The method of claim 10 , wherein:
the width of the program pulse applied to the set of memory cells is based on a number of memory cells for which reprogramming is warranted.

13. The method of claim 1 , wherein:
after the completion criterion is met for the one programming pass, obtaining a measure of a width of a threshold voltage distribution of at least one of the target data states, wherein for the at least one of the target data states, the width of the program pulse applied to the set of memory cells during the program-verify iterations in the reprogramming pass is based on the measure of the width of the threshold voltage distribution.

14. A memory device, comprising:
a set of memory cells comprising respective subsets of memory cells, each respective subset of memory cells has a respective target data state defined by a respective verify voltage; and
a control circuit, the control circuit configured to:
perform a plurality of program-verify iterations in one programming pass for the set of memory cells until a completion criterion is met for the one programming pass, wherein the completion criterion is met when at least a specified percentage of memory cells of each set of memory cells has a threshold voltage which is above the respective verify voltage,
after the completion criterion is met for the one programming pass, identify memory cells of each respective target data state for which reprogramming is warranted by performing a verify test to identify memory cells of each respective target data state having a threshold voltage which exceeded and then fell below a respective verify voltage, and
perform a plurality of program-verify iterations in a reprogramming pass for the memory cells of each respective target data state for which reprogramming is warranted, wherein a width of a program pulse applied to the set of memory cells during the program-verify iterations in the reprogramming pass is longer than a width of a program pulse applied to the set of memory cells during the program-verify iterations in the one programming pass.

15. The memory device of claim 14 , wherein:
the plurality of program-verify iterations in the reprogramming pass comprises a separate set of program-verify iterations for each respective target data state;
the width of the program pulse applied to the set of memory cells during the program-verify iterations in the reprogramming pass comprise a different width for each of the separate sets of program verify iterations; and
the different widths are greater for relatively higher target data states among the respective target data states than for relatively lower target data states among the respective target data states.

16. The memory device of claim 14 , wherein:
the plurality of program-verify iterations in the reprogramming pass are common to each respective target data state.

17. The memory device of claim 14 , wherein:
the set of memory cells comprise ch

Assignees

• Sandisk Technologies Inc

Inventors

• Pang Liang
• Dong Yingda

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C2211/5621

  Multilevel programming verification · CPC title