Handling unaligned load operations in a multi-slice computer processor

Patent metadata

Field	Value
Publication number	US-10067763-B2
Application number	US-201514966075-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Dec 11, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

First claim

What is claimed is:

1. A multi-slice computer processor, the multi-slice computer processor configured for:
receiving a request to load data stored within a range of addresses;
determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice;
issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses;
executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice;
receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each of the plurality of data communications busses is associated with one of the distinct processor slices; and
assembling, from the execution results from each distinct processor slice, the data stored within the range of addresses, including: identifying a portion of each execution result that includes data stored within the range of addresses; and
combining the portion of each execution result that includes data stored within the range into a single result.

2. The multi-slice computer processor of claim 1 further configured for formatting, by each processor slice, the execution results.

3. The multi-slice computer processor of claim 2 wherein formatting, by each processor slice, the execution results further comprises:
identifying a portion of the execution results that includes data contained in the range of addresses;
determining whether the portion of the execution results that includes data contained in the range of addresses represents a beginning portion of the range of addresses or an ending portion of the range of addresses; and
shifting, in dependence upon whether the portion of the execution results that includes data contained in the range of addresses represents a beginning portion of the range of addresses or an ending portion of the range of addresses, the portion of the execution results that includes data contained in the range of addresses.

4. The multi-slice computer processor of claim 1 further configured for predicting when the data stored within the range of addresses will be loaded into a target memory location.

5. The multi-slice computer processor of claim 4 further configured for:
identifying one or more operations that are dependent upon completion of the request to load data stored within the range of addresses; and
issuing, in dependence upon when the data stored within the range of addresses is predicted to be loaded into the target memory location, the one or more operations that are dependent upon completion of the request to load data stored within the range of addresses.

6. A computing system, the computing system including a multi-slice computer processor, the multi-slice computer processor configured for:
receiving a request to load data stored within a range of addresses;
determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice;
issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses;
executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice;
receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each of the plurality of data communications busses is associated with one of the distinct processor slices; and
assembling, from the execution results from each distinct processor slice, the data stored within the range of addresses, including: identifying a portion of each execution result that includes data stored within the range of addresses; and
combining the portion of each execution result that includes data stored within the range into a single result.

7. The computing system of claim 6 , wherein the multi-slice computer processor is further configured for formatting, by each processor slice, the execution results.

8. The computing system of claim 7 wherein formatting, by each processor slice, the execution results further comprises:
identifying a portion of the execution results that includes data contained in the range of addresses;
determining whether the portion of the execution results that includes data contained in the range of addresses represents a beginning portion of the range of addresses or an ending portion of the range of addresses; and
shifting, in dependence upon whether the portion of the execution results that includes data contained in the range of addresses represents a beginning portion of the range of addresses or an ending portion of the range of addresses, the portion of the execution results that includes data contained in the range of addresses.

9. The computing system of claim 6 , wherein the multi-slice computer processor is further configured for:
predicting when the data stored within the range of addresses will be loaded into a target memory location;
identifying one or more operations that are dependent upon completion of the request to load data stored within the range of addresses; and
issuing, in dependence upon when the data stored within the range of addresses is predicted to be loaded into the target memory location, the one or more operations that are dependent upon completion of the request to load data stored within the range of addresses.

Assignees

• IBM

Inventors

• Chadha Sundeep
• Cordes Robert A
• Hrusecky David A
• Le Hung Q
• Leenstra Jentje
• Nguyen Dung Q
• Thompto Brian W
• Van Norstrand Jr Albert J

Classifications

• G06F9/3891

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title