Apparatuses, methods, and systems for memory disambiguation

Patent metadata

Field	Value
Publication number	US-10067762-B2
Application number	US-201615201218-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

First claim

What is claimed is:

1. A processor comprising:
a decoder to decode an instruction into a decoded instruction;
an execution unit to execute the decoded instruction;
a retirement unit to retire an executed instruction in program order; and
a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction,
wherein the memory disambiguation circuit is, for a second load instruction to be executed, to compare an instruction pointer for the second load instruction to the instruction pointer for the first load instruction and when there is a match and the counter value exceeds a threshold value, to prevent the second load instruction from bypassing an older store instruction without an access address, and wherein after the second load instruction is executed, the memory disambiguation circuit is to increment the counter value when the second load instruction bypassed an older store instruction that is to write data that the second load instruction is to consume, and decrement the counter value when the second load instruction bypassed an older store instruction that is not to write data that the second load instruction is to consume.

2. The processor of claim 1 , wherein the memory disambiguation circuit is to allocate the entry in the memory disambiguation table for the first load instruction at retirement of the first load instruction by the retirement unit.

3. The processor of claim 1 , wherein the memory disambiguation circuit is to not change the counter value when the second load instruction did not bypass an older store instruction.

4. The processor of claim 1 , wherein the memory disambiguation circuit is to decrement and increment the counter value after the second load instruction is executed but before the second load instruction is retired by the retirement unit.

5. The processor of claim 1 , wherein the memory disambiguation circuit is to set a bit on the second load instruction before it is executed to cause a decrement and an increment of the counter value.

6. The processor of claim 1 , wherein the memory disambiguation circuit is to set the counter value to a maximum value when the entry is allocated.

7. A method comprising:
decoding an instruction into a decoded instruction with a decoder of a processor;
executing the decoded instruction with an execution unit of the processor;
retiring an executed instruction in program order with a retirement unit of the processor;
allocating, with a memory disambiguation circuit, an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction; and
comparing, with the memory disambiguation circuit for a second load instruction to be executed, an instruction pointer for the second load instruction to the instruction pointer for the first load instruction and when there is a match and the counter value exceeds a threshold value, preventing the second load instruction from bypassing an older store instruction without an access address, and wherein after the second load instruction is executed, the memory disambiguation circuit is to increment the counter value when the second load instruction bypassed an older store instruction that is to write data that the second load instruction is to consume, and decrement the counter value when the second load instruction bypassed an older store instruction that is not to write data that the second load instruction is to consume.

8. The method of claim 7 , wherein the allocating comprises allocating the entry in the memory disambiguation table for the first load instruction at retirement of the first load instruction by the retirement unit.

9. The method of claim 7 , further comprising not changing the counter value when the second load instruction did not bypass an older store instruction.

10. The method of claim 7 , further comprising decrementing and incrementing the counter value after the second load instruction is executed but before the second load instruction is retired by the retirement unit.

11. The method of claim 7 , further comprising setting a bit on the second load instruction before it is executed to cause a decrement and an increment of the counter value.

12. The method of claim 7 , further comprising setting the counter value to a maximum value when the entry is allocated.

13. A processor comprising:
a decoder to decode an instruction into a decoded instruction;
an execution unit to execute the decoded instruction;
a retirement unit to retire an executed instruction in program order; and
a memory disambiguation circuit to allocate a first entry in a memory disambiguation table for a single load and store pair of instructions that are to be flushed for a memory ordering violation, the first entry comprising a counter value and an instruction pointer for a load instruction of the single load and store pair of instructions, and allocate a second entry in the memory disambiguation table for multiple load instructions and a single store instruction that are to be flushed for a memory ordering violation, the second entry comprising a counter value and an instruction pointer for the single store instruction.

14. The processor of claim 13 , wherein the memory disambiguation circuit is, for an additional instruction to be executed, to compare an instruction pointer for the additional instruction to the instruction pointers in the memory disambiguation table and when there is a match and a respective counter value exceeds a threshold value, to prevent younger load instructions without an access address from bypassing a store type of the additional instruction, and prevent a load type of the additional instruction from bypassing an older store instruction without an access address.

15. The processor of claim 13 , wherein the memory disambiguation circuit is, after a load type of an additional instruction is executed, to increment a respective counter value when the additional instruction bypassed an older store instruction that is to write data that the additional instruction is to consume, and decrement the respective counter value when the additional instruction bypassed an older store instruction that is not to write data that the additional instruction is to consume.

16. The processor of claim 15 , wherein the memory disambiguation circuit is to not change the respective counter value when the additional instruction did not bypass an older store instruction.

17. The processor of claim 13 , wherein the memory disambiguation circuit is, after a store type of an additional instruction is executed, to increment a respective counter value when a younger load instruction is to consume data written by the additional instruction, and decrement the respective counter value when all younger load instructions with an access address are not to read data that the additional instruction is to write.

18. The processor of claim 17 , wherein the memory disambiguation circuit is to not change the respective counter value when there are no load instructions with an access address.

19. A method comprising:
decoding an instruction into a decoded instruction with a decoder of a processor;
executing the decoded instruction with an execution unit of the processor;
retiring an executed instruction in program order w

Assignees

• Intel Corp

Inventors

• Agarwal Vikash
• Bryant Christopher D
• Combs Jonathan D
• Robinson Stephen J

Classifications

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title