Checkpoints associated with an out of order architecture

Patent metadata

Field	Value
Publication number	US-9256497-B2
Application number	US-201414224233-A
Country	US
Kind code	B2
Filing date	Mar 25, 2014
Priority date	Mar 25, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction.

First claim

What is claimed is:

1. A processor comprising:
a memory;
a memory channel coupled to the memory; and
an at-retirement checkpoint module, coupled to the memory through the memory channel, to:
receive an instruction;
identify if the instruction is associated with a first type of speculative error or is not associated with the first type of speculative error;
perform a first operation if the instruction is associated with the first type of speculative error, wherein the firs…

Assignees

• Khartikov Denis M
• Kelm John H
• Neelakantam Naveen
• Intel Corp

Inventors

• Khartikov Denis M
• Kelm John H
• Neelakantam Naveen

Classifications

• G06F9/384 Primary

  Physics · mapped topic

• G06F9/30145 Primary

  Physics · mapped topic

• G06F11/1435 Primary

  Physics · mapped topic

• G06F9/3863

  Physics · mapped topic

• G06F9/3842

  Physics · mapped topic