Band-gap reference circuit

Patent metadata

Field	Value
Publication number	US-10067518-B2
Application number	US-201615366267-A
Country	US
Kind code	B2
Filing date	Dec 1, 2016
Priority date	Apr 27, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A band-gap reference circuit including: mirror current branch circuits, band-gap paths, and an operational amplifier. Each mirror current branch circuit includes a mirror PMOS transistor and an auxiliary PMOS transistor. A drain of each mirror PMOS transistor is connected with a source of a corresponding auxiliary PMOS transistor, and a drain of said each auxiliary PMOS transistor is connected to a top end of a corresponding band-gap path, each gate of each mirror PMOS transistor is connected with an output port of the operational amplifier. A gate of each auxiliary PMOS transistor is connected to a first bias voltage. A substrate electrode of each mirror and auxiliary transistor is all connected to a source voltage. The output port of the operational amplifier outputs a high level less than the source voltage, the first bias voltage is less than an output voltage signal of the operational amplifier.

First claim

What is claimed is:

1. A band-gap reference circuit, comprising: three mirror current branch circuits, three band-gap paths, and an operational amplifier;
the three band-gap paths form a temperature-irrelevant reference voltage by means of superposition of a base-emitter voltage and of a base-emitter voltage difference of a diode-connected bipolar transistor, wherein the base-emitter voltage and the base-emitter voltage difference have opposite temperature coefficients;
a bottom end of said each band-gap path is grounded, a top end of said each band-gap path is connected with a source voltage via one of the mirror current branch circuits, and said each mirror current branch circuit comprises a mirror PMOS transistor and an auxiliary PMOS transistor;
said each mirror PMOS transistor of said each mirror current branch circuit is a mirror image of each other, and a source of said each mirror PMOS transistor of said each mirror current branch circuit is connected with the source voltage; a drain of said each mirror PMOS transistor of said each mirror current branch circuit is connected with a source of the corresponding auxiliary PMOS transistor, and a drain of said each auxiliary PMOS transistor is connected to the top end of the corresponding band-gap path;
a third band-gap path of the three band-gap paths is designated as an output path, the top end of the third band-gap path outputs a reference voltage; the top end of a first band-gap path and the top end of a second band-gap path of the three band-gap paths are respectively connected to an input port of the operational amplifier;
a gate of said each mirror PMOS transistor of said each mirror current branch circuit is connected to an output port of the operational amplifier; each gate of said each auxiliary PMOS transistor of said each mirror current branch circuit is connected together and is connected with a first bias voltage;
a substrate electrode of said each mirror PMOS transistor of said each mirror current branch circuit and a substrate electrode of said each auxiliary PMOS transistor of said each mirror current branch circuit are connected to the source voltage;
the output port of the operational amplifier outputs a high level which is less than the source voltage, the first bias voltage is less than an output voltage of the operational amplifier, and during operation of the band-gap reference circuit, the auxiliary PMOS transistor enables a drain voltage of the mirror PMOS transistor to rise high enough so that a gate-drain voltage difference of the mirror PMOS transistor is less than a value enabling a substrate leakage current of the mirror PMOS transistor to rise at a rate substantially in order of nanoamperes per volt, and at the meantime, a corresponding gate-drain voltage difference of the auxiliary PMOS transistor is less than a value enabling a substrate leakage current of the auxiliary PMOS transistor to rise substantially at a rate in order of nanoamperes per volt.

2. The band-gap reference circuit of claim 1 , wherein
the operational amplifier has a foldable, differential, common-source and common-gate main body amplifying circuit, wherein a first NMOS transistor and a second NMOS transistor constitute two differential input common-source amplifying transistors, a first PMOS transistor and a second PMOS transistor constitute two common-gate amplifying transistors, a drain of the second PMOS transistor is the output port of the operational amplifier, a source of the first PMOS transistor and a source of the second PMOS transistor are respectively connected with a current source circuit consisting of a PMOS transistor, and a drain of the first PMOS transistor is connected with a load circuit by a second auxiliary PMOS transistor; a substrate electrode of the first PMOS transistor and a substrate electrode of the corresponding auxiliary PMOS transistor are both connected to the source voltage; a gate of the auxiliary PMOS transistor corresponding to the first PMOS transistor is connected with the first bias voltage, during operation of the band-gap reference circuit, the auxiliary PMOS transistor enables a drain voltage of the mirror PMOS transistor to rise high enough that a corresponding gate-drain voltage difference of the mirror PMOS transistor is less than a value enabling a substrate leakage current of the mirror PMOS transistor to rise substantially at a rate in order of nanoamperes per volt, and at the meantime, a corresponding gate-drain voltage difference of the auxiliary PMOS transistor is less than a value enabling a substrate leakage current of the auxiliary PMOS transistor to rise substantially at a rate in order of nanoamperes per volt.

3. The band-gap reference circuit of claim 2 , wherein,
the gate-drain voltage difference of the mirror PMOS transistor and a gate-drain voltage difference of the first PMOS transistor are both less than 3v, and the gate-drain voltage difference of the auxiliary PMOS transistor is also less than 3v.

4. The band-gap reference circuit of claim 2 , wherein, a source of the first NMOS transistor and a source of the second NMOS transistor are both connected to a drain of a third NMOS transistor acting as a current source, a source of the third NMOS transistor is grounded, and a gate of the third NMOS transistor is connected with a second bias voltage;
the first bias voltage is provided by a first bias circuit, the first bias circuit comprises a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, a drain of the sixth NMOS transistor is connected with the source voltage, a gate of the sixth NMOS transistor is connected to the output port of the operational amplifier; a source of the sixth NMOS transistor is connected with a drain and a gate of the fifth NMOS transistor, a source of the fifth NMOS transistor is connected with a drain of the fourth NMOS transistor, a source and a substrate electrode of the fourth NMOS transistor, a substrate electrode of the fifth NMOS transistor, and a substrate electrode of the sixth NMOS transistor are all grounded; a gate of the fourth NMOS transistor is connected with the second bias voltage, and a drain of the fourth NMOS transistor provides the first bias voltage.

5. The band-gap reference circuit of claim 2 , wherein,
the load circuit corresponding to the first PMOS transistor comprises a seventh NMOS transistor and an eighth NMOS transistor, the second PMOS transistor corresponds to another load circuit comprising a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor, a drain of the seventh NMOS transistor; a drain of the auxiliary PMOS transistor corresponding to the first PMOS transistor, a gate of the eighth NMOS transistor, and a gate of the eleventh NMOS transistor are connected together; a gate of the seventh NMOS transistor, a gate of the tenth NMOS transistor, and a gate of the ninth NMOS transistor are all connected with a third bias voltage; a source of the seventh NMOS transistor is connected with a drain of the eighth NMOS transistor, and a source of the eighth NMOS transistor is grounded;
a drain of the ninth NMOS transistor is connected with a drain of the second PMOS transistor, a source and a substrate electrode of the ninth NMOS transistor are connected with a drain of the tenth NMOS transistor; a source of the tenth NMOS transistor is connected with a drain of the eleventh NMOS transistor, and a source of the eleventh NMOS transistor is grounded;
a substrate electrode of the seventh NMOS transistor, a substrate electrode of the eighth NMOS transistor, a substrate electrode of the tenth NMOS transistor, and a substrate electrode of the eleventh NMOS transistor are all grounded.

6. The band-gap reference circuit of claim 1 , wherein the gate-drain voltage difference of the mirror PMOS

Assignees

• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Tang Chengwei

Classifications

• G05F1/625

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• G05F1/461 Primary

  using an operational amplifier as final control device · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• H03K17/60

  the devices being bipolar transistors (bipolar transistors having four or more electrodes H03K17/72) · CPC title