Mask read-only memory device

Patent metadata

Field	Value
Publication number	US-10062702-B2
Application number	US-201815868098-A
Country	US
Kind code	B2
Filing date	Jan 11, 2018
Priority date	Jan 7, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A mask read-only memory (M-ROM) device is provided. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

First claim

What is claimed is:

1. A mask read-only memory device, comprising:
a first substrate including a first region and a second region;
a first layer having a first type doping in the first region of the first substrate;
a second substrate on the first region and the second region of the first substrate;
a first isolation structure in the second substrate and partially in the first substrate between the first region and the second region;
a plurality of diodes in the second substrate and on the first layer of the first substrate, wherein the plurality of diodes are arranged in an array and each diode comprises a first electrode having a second type doping and connecting with a buried line, and a second electrode having the first type doping and located on the first electrode; and
a metal-oxide-semiconductor (MOS) transistor in the second substrate above the second region of the first substrate.

2. The mask read-only memory device of claim 1 , further comprising:
a plurality of second isolation structures in the second substrate to isolate the plurality of diodes from each other in a first direction.

3. The mask read-only memory device of claim 2 , wherein:
each second isolation structure comprises a shallow trench having a depth no less than a thickness of the plurality of diodes.

4. The mask read-only memory device of claim 1 , further comprising:
a plurality of bit lines corresponding to the plurality of buried lines above the second layer of the substrate, wherein:
the plurality of bit lines are arranged in parallel in the first direction, and
each bit line is electrically connected with a corresponding buried line; and

a plurality of word lines arranged in parallel in the second direction, wherein one of the plurality of word lines is selectively connected with a second electrode of a diode under the one of the plurality of word lines.

5. The mask read-only memory device of claim 1 , further comprising:
a plurality of lead regions in the first region of the second substrate, wherein:
the lead regions have the first type doping.

6. The mask read-only memory device of claim 5 , wherein the first isolation structure isolates the plurality of lead regions and the first layer from a well region of the MOS transistor.

7. The mask read-only memory device of claim 1 , wherein the MOS transistor comprises:
a well region of the MOS transistor in the second layer substrate, wherein:
the well region has a second type doping, and

a gate electrode of the MOS transistor on the well region; and
a source electrode and a drain electrode of the MOS transistor in the well region, wherein the source electrode and the drain electrode have a first type doping.

8. The mask read-only memory device of claim 7 , further comprising:
forming a third isolation structure in the second region of the second substrate to isolate the well region and the lead region,
wherein the plurality of second isolation structures and the third isolation structure are formed in a same process.

9. The mask read-only memory device of claim 1 , wherein the first substrate further includes a third layer having a second type doping, and the first layer is formed on the third layer.

10. The mask read-only memory device of claim 9 , wherein the first isolation structure extends into the third layer of the first substrate.

11. The mask read-only memory device of claim 1 , wherein the first type doping is N-type ions doping, and the second type doping is P-type ions doping.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhang Chao
• Chan Yipeng

Classifications

• H01L27/112

  Electricity · mapped topic

• H01L27/11253 Primary

  Electricity · mapped topic

• H10B20/38 Primary

  Doping programmed, e.g. mask ROM · CPC title

• H10B20/00

  Read-only memory [ROM] devices · CPC title