Composite bond structure in stacked semiconductor structure

Patent metadata

Field	Value
Publication number	US-10062656-B2
Application number	US-201615236526-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Aug 15, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a dielectric structure disposed on the substrate;
a top metal layer disposed in the dielectric structure; and
a bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:
a silicon oxide layer disposed on the dielectric structure;
a silicon oxy-nitride layer covering the silicon oxide layer, wherein the silicon oxide layer has a high density plasma chemical vapor deposition portion in direct contact with the silicon oxy-nitride layer;
a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; and
a barrier layer covering a sidewall and a bottom of the conductive bonding layer.

2. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation, a top surface of the silicon oxy-nitride layer is at a second elevation, and the first elevation is higher than the second elevation.

3. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation, a top surface of the silicon oxy-nitride layer is at a second elevation, and the first elevation is lower than the second elevation.

4. The semiconductor device of claim 1 , wherein the conductive bonding layer is a redistribution layer.

5. The semiconductor device of claim 1 , further comprising an etch stop layer disposed between the dielectric structure and the bonding structure, wherein the barrier layer is disposed in the etch stop layer.

6. The semiconductor device of claim 5 , wherein the etch stop layer is formed from silicon nitride.

7. A semiconductor device, comprising:
a first semiconductor structure comprising:
a first substrate;
an etch stop layer over the first substrate; and
a first bonding structure disposed over the etch stop layer, and the first bonding structure comprising:
a first silicon oxide layer disposed over the first substrate;
a first silicon oxy-nitride layer covering the first silicon oxide layer, wherein the first silicon oxide layer has a high density plasma chemical vapor deposition portion extending from the first silicon oxy-nitride layer to the etch stop layer;
a first conductive bonding layer disposed in the first silicon oxide layer and the first silicon oxy-nitride layer; and
a first barrier layer covering a sidewall and a bottom of the first conductive bonding layer; and
a second semiconductor structure comprising:
a second substrate; and
a second bonding structure disposed over the second substrate and bonded to the first bonding structure, wherein the second bonding structure comprises a second conductive bonding layer which is disposed in the second bonding structure and is bonded to the first conductive bonding layer.

8. The semiconductor device of claim 7 , wherein a top surface of the first conductive bonding layer is at a first elevation, a top surface of the first silicon oxy-nitride layer is at a second elevation, and the first elevation is higher than the second elevation.

9. The semiconductor device of claim 7 , wherein a top surface of the first conductive bonding layer is at a first elevation, a top surface of the first silicon oxy-nitride layer is at a second elevation, and the first elevation is lower than the second elevation.

10. The semiconductor device of claim 7 , wherein the first semiconductor structure further comprises:
a first dielectric structure disposed on the first substrate; and
a first top metal layer disposed in the first dielectric structure, wherein the first bonding structure is disposed on the first dielectric structure and the first top metal layer.

11. The semiconductor device of claim 7 , wherein the second semiconductor structure further comprises:
a second dielectric structure disposed on the second substrate; and
a second top metal layer disposed in the second dielectric structure, wherein the second bonding structure is disposed on the second dielectric structure and the second top metal layer.

12. The semiconductor device of claim 11 , wherein the second bonding structure further comprises:
a second silicon oxide layer disposed on the second substrate;
a second silicon oxy-nitride layer covering the second silicon oxide layer; and
a second barrier layer covering a sidewall and a bottom of the second conductive bonding layer, wherein the second barrier layer and the second conductive bonding layer is disposed in the second silicon oxide layer and the second silicon oxy-nitride layer.

13. The semiconductor device of claim 12 , wherein a top surface of the second conductive bonding layer is at a third elevation, a top surface of the second silicon oxy-nitride layer is at a fourth elevation, and the third elevation is higher than or lower than the fourth elevation.

14. The semiconductor device of claim 1 , wherein the silicon oxy-nitride layer has an extinction coefficient substantially ranging from 0.4 to 0.6.

15. The semiconductor device of claim 1 , wherein the barrier layer conformally covers the sidewall and the bottom of the conductive bonding layer.

16. The semiconductor device of claim 5 , wherein the conductive bonding layer is separated from the silicon oxide layer, the silicon oxy-nitride layer, the etch stop layer, and the top metal layer by the barrier layer.

17. The semiconductor device of claim 7 , wherein the first silicon oxy-nitride layer has a reflectivity substantially ranging from 2.0 to 2.4, and an extinction coefficient substantially ranging from 0.4 to 0.6.

18. The semiconductor device of claim 7 , wherein the first barrier layer conformally covers the sidewall and the bottom of the first conductive bonding layer.

19. The semiconductor device of claim 7 , wherein the first conductive bonding layer is separated from the first silicon oxide layer, the first silicon oxy-nitride layer, and the first substrate by the first barrier layer.

20. A semiconductor device, comprising:
a substrate;
a dielectric structure disposed on the substrate;
a top metal layer disposed in the dielectric structure; and
a bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:
a silicon oxide layer disposed on the dielectric structure, wherein an entirety of the silicon oxide layer is a high density plasma chemical vapor deposition layer;
a silicon oxy-nitride layer covering the silicon oxide layer and physically contacting the silicon oxide layer;
a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; and
a barrier layer covering a sidewall and a bottom of the conductive bonding layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chao-Ching
• Li Sheng-Chan
• Tsai Wen-Jen
• Huang Chih-Hui
• Tsai Jian-Shin
• Wu Cheng-Yi
• Lin Yi-Ming
• Lin Min-Hui

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title