Cell library and method for designing an asynchronous integrated circuit

Patent metadata

Field	Value
Publication number	US-9430600-B2
Application number	US-201314395344-A
Country	US
Kind code	B2
Filing date	Apr 22, 2013
Priority date	May 4, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An asynchronous integrated circuit is designed from a library of cells comprising at least one cell having parameters of signal propagation between a first terminal and a second terminal and between the second terminal and a third terminal depending on the parameter of signal propagation between the first and the third terminal. A synchronous integrated circuit corresponding to the asynchronous integrated circuit is synthesized using said cell to represent a portion of the asynchronous circuit, said cell being rated by a dummy clock signal. The synthesized integrated circuit is verified using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

First claim

The invention claimed is:

1. A method comprising steps of:
providing, in a synchronous integrated circuit design assistance tool implemented by a computer, a library of cells comprising at least one cell having parameters of signal propagation between a first terminal (A) and a second terminal (R) and between the second terminal (R) and a third terminal (Z) depending on the parameter of signal propagation between the first and the third terminal;
synthesizing, in the synchronous integrated circuit design assistance tool implemented by a computer, a synchronous integrated circuit corresponding to the asynchronous integrated circuit by using said cell to represent a portion of the asynchronous circuit, and wherein said cell is rated by a dummy clock signal supplied to the second terminal; and
verifying, in the synchronous integrated circuit design assistance tool implemented by a computer, the synthesized integrated circuit by using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

2. The method of claim 1 , wherein the library comprises, for said cell, an indication that the second terminal (R) is intended to receive the dummy clock signal during the design of the asynchronous integrated circuit by a synchronous integrated circuit design assistance tool.

3. The method of claim 1 , wherein the cell is representative of a portion of the asynchronous circuit, the second terminal (R) being intended, in operation, to receive a signal (Reset) for resetting the circuit portion.

4. The method of claim 1 , wherein the cell is representative of a portion of the asynchronous circuit, where the second terminal (R) does not correspond to a physical terminal of the portion intended, in operation, to deliver or to receive signals.

5. The method of claim 1 , wherein the cell comprises a first parameter of signal propagation from the first terminal (A) to the second terminal (R) and a second parameter of signal propagation from the second terminal to the third terminal (Z), the first and second parameters being obtained from a third parameter of signal propagation from the first terminal to the third terminal, wherein the third parameter corresponds to an array of elements D i,j r(A→Z) where i is an integer varying from 1 to P and j is an integer varying from 1 to Q, wherein the second parameter corresponds to an array of elements {circumflex over (D)} j r(R→Z) obtained according to the following relation:
{circumflex over (D)} j r(R→Z) =D I,j r(A→Z)
I being a natural integer selected between 1 and P, and wherein the first parameter corresponds to an array of elements Ŝ i r(A→R) obtained according to the following relation:
Ŝ i r(A→R) =D i,j r(A→Z) −{circumflex over (D)} J r(A→Z)

J being a natural integer selected between 1 and Q.

6. The method of claim 2 , wherein the cell further comprises a fourth terminal (B), a fourth parameter of signal propagation from the fourth terminal to the third terminal (Z) corresponding to an array of elements D i,j r(B→Z) , the library further comprising a fifth parameter of signal propagation from the fourth terminal to the second terminal (R), the fifth parameter corresponding to an array of elements Ŝ i r(B→R) obtained according to the following relation:
Ŝ i r(B→R) =D i,J r(B→Z) −{circumflex over (D)} J r(R→Z) +Margin
where Margin is a real number greater than or equal to zero, which is constant independently from i or which depends on the transition time of the dummy clock signal on the second terminal.

7. The method of claim 5 , wherein the first terminal (A) is, in operation, a terminal of reception of a first signal alternating between two states, wherein the third terminal (Z) is, in operation, a terminal of provision of a second signal alternating between two states and wherein the third parameter corresponds to the time between a state switching of the first signal and a state switching of the second signal.

8. The method of claim 1 , wherein the second terminal (R) corresponds to the terminal of the portion of the asynchronous circuit intended, in operation, to receive a signal (Reset) for resetting said portion of the asynchronous circuit, the method comprising a step of designing a clock tree to transmit the dummy clock signal to said portion of the asynchronous circuit, the clock tree being used in operation as a network for the distribution of the reset signal to said portion of the asynchronous circuit.

9. The method of claim 1 , wherein the verification step is carried out with an asynchronous model to simulate the operation of said portion of the asynchronous circuit.

10. Non-transitory computer-readable storage means storing a computer program comprising a set of instructions executable by a computer to implement the method of claim 1 .

11. Non-transitory computer-readable storage means storing a cell library to implement the method of claim 1 .

Assignees

• Commissariat Energie Atomique
• Commissariat à l'Energie Atomique et aux Energies Alternatives

Inventors

• Thonnart Yvain
• Vivet Pascal

Classifications

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/35 Primary

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• G06F13/4009

  with data restructuring · CPC title

• G06F30/30

  Circuit design · CPC title