Radio frequency voltage-to-current converting circuit and method

Patent metadata

Field	Value
Publication number	US-10061333-B1
Application number	US-201715619487-A
Country	US
Kind code	B1
Filing date	Jun 11, 2017
Priority date	May 16, 2017
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A voltage-to-current converting circuit, comprising: a direct current (DC) bias circuit, a first DC-blocking circuit, a second DC-blocking circuit, a first differential input pair and a second differential input pair; wherein the DC bias circuit is connected to the first and second DC-blocking circuits and configured to provide a bias voltage to the first and the second differential input pairs; wherein the first DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair and the second DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair; and wherein the first differential circuit is connected to the second differential circuit via two resistors.

First claim

What is claimed is:

1. A voltage-to-current converting circuit, comprising:
a direct current (DC) bias circuit, a first DC-blocking circuit, a second DC-blocking circuit, a first differential input pair and a second differential input pair, wherein the DC bias circuit comprises a first resistor, a second resistor, a first MOS transistor and a second MOS transistor,
a first node of the first resistor is connected to a first node of the first MOS transistor, and a first node of the second resistor is connected to a first node of the second MOS transistor, and wherein resistance of the first resistor is equal to resistance of the second resistor, and
any two of a second node of the first MOS transistor, a second node of the second MOS transistor, a second node of the first resistor and a second node of the second resistor are connected, and

wherein the DC bias circuit further comprises a first current source and a second current source,
the first current source is connected between the first node of the first resistor and the first node of the first MOS transistor, wherein a first node of the first current source is connected to the first node of the first resistor and a power supply, and a second node of the first current source is connected to the first node of the first MOS transistor and a third node of the first MOS transistor, and the second current source is connected between the first node of the second resistor and the first node of the second MOS transistor, wherein a first node of the second current source is connected to the first node of the second resistor and ground, and a second node of the second current source is connected to the first node of the second MOS transistor and a third node of the second MOS transistor;
wherein the DC bias circuit is connected to the first and second DC-blocking circuits and configured to provide a bias voltage to the first and the second differential input pairs;
wherein the first DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pairs and the second DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pairs; and
wherein the first differential circuit is connected to the second differential circuit via two resistors.

2. The voltage-to-current converting circuit of claim 1 , wherein the first DC-blocking circuit comprises a first capacitor, a second capacitor, a third resistor and a fourth resistor;
wherein a first node of the first capacitor and a first node of the second capacitor are connected and also configured to receive a positive input; a second node of the first capacitor is connected to a second node of the third resistor; a second node of the second capacitor is connected to a second node of the fourth resistor; and
wherein any two of a first node of the third resistor, the first node of the first MOS transistor, the third node of the first MOS transistor and the second node of the first current source are connected, and any two of a first node of the fourth resistor, the first node of the second MOS transistor, the third node of the second MOS transistor and the second node of the second current source are connected.

3. The voltage-to-current converting circuit of claim 2 , wherein the second DC-blocking circuit comprises a third capacitor, a fourth capacitor, a fifth resistor and a sixth resistor;
wherein a first node of the third capacitor and a first node of the fourth capacitor are connected and also configured to receive a negative input; a second node of the third capacitor is connected to a second node of the fifth resistor; a second node of the fourth capacitor is connected to a second node of the sixth resistor; and
wherein any two of a first node of the fifth resistor, the first node of the third resistor, the first node of the first MOS transistor, the third node of the first MOS transistor and the second node of the first current source are connected, and any two of a first node of the sixth resistor, the first node of the fourth resistor, the first node of the second MOS transistor, the third node of the second MOS transistor and the second node of the second current source are connected.

4. The voltage-to-current converting circuit of claim 3 , wherein the first differential input pair comprises a third MOS transistor and a fourth MOS transistor;
wherein any two of a first node of the third MOS transistor, the first node of the first current source, the first node of the first resistor and the power supply are connected, and a third node of the third MOS transistor is connected to both second nodes of the third resistor and the first capacitor; and
wherein any two of a first node of the fourth MOS transistor, the first node of the third MOS transistor, the first node of the first current source, the first node of the first resistor and the power supply are connected, and a third node of the fourth MOS transistor is connected to both second nodes of the fifth resistor and the third capacitor.

5. The voltage-to-current converting circuit of claim 4 , wherein the second differential input pair comprises a fifth MOS transistor and a sixth MOS transistor;
wherein any two of a first node of the fifth MOS transistor, the first node of the second current source, the first node of the second resistor are connected and connected to ground, and a third node of the fifth MOS transistor is connected to both second nodes of the fourth resistor and the second capacitor; and
wherein any two of a first node of the sixth MOS transistor, the first node of the fifth MOS transistor, the first node of the second current source, the first node of the second resistor are connected and connected to ground, and a third node of the sixth MOS transistor is connected to both second nodes of the sixth resistor and the fourth capacitor.

6. The voltage-to-current converting circuit of claim 5 , wherein the first differential input pair is connected to the second differential input pair via a seventh resistor and an eighth resistor;
wherein a first node of the seventh resistor is connected to a first node of the eighth resistor and a second node of the seventh resistor is connected to both second nodes of the third MOS transistor and the fifth MOS transistor;
wherein a second node of the eighth resistor is connected to both second nodes of the fourth MOS transistor and the sixth MOS transistor; and
wherein both first nodes of the seventh resistor and eighth resistor are connected to a first node of a voltage source and any two of a second node of the voltage source, the first node of the sixth MOS transistor, the first node of the fifth MOS transistor, the first node of the second current source, the first node of the second resistor are connected and connected to ground.

7. The voltage-to-current converting circuit of claim 6 , wherein the first, the third and the fourth MOS transistors are NMOS transistors, the second, the fifth and the sixth MOS transistors are PMOS transistors; and
the first node of each of the transistors is a drain, the second node of each of the transistors is a source, and the third node of each of the transistors is a gate.

8. A method for converting voltage to current by a voltage-to-current converting circuit, wherein the circuit comprises: a direct current (DC) bias circuit, a first DC-blocking circuit, a second DC-blocking circuit, a first differential input pair and a second differential input pair, wherein the DC bias circuit comprises a first resistor, a second resistor, a first MOS transistor and a second MOS transistor,
a first node of the first resistor is connected to a first node of the first MOS transistor, and a first node of the second resistor is

Assignees

• Beken Corp

Inventors

• Liu Jiazhou
• Guo Dawei

Classifications

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title