Analog/digital conversion with analog filtering

Patent metadata

Field	Value
Publication number	US-10056916-B2
Application number	US-201715675091-A
Country	US
Kind code	B2
Filing date	Aug 11, 2017
Priority date	Sep 16, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.

First claim

The invention claimed is:

1. A circuit comprising:
an input terminal configured to receive an analog input signal,
a combination element comprising a number of sample-and-hold elements configured to sample and to hold a number of time-displaced signal values of the analog input signal at different times, wherein the combination element is configured to combine the time-displaced signal values of the analog input signal to form an analog combination signal, and
a quantizer having a converter core configured to receive the analog combination signal via passive charge redistribution from the combination element and to convert it into a digital output signal.

2. The circuit of claim 1 ,
wherein the sample-and-hold elements comprise at least one switch and in each case one capacitor,
wherein the circuit also comprises at least one controller configured to combine the time-displaced signal values of the analog input signal by time-overlapping operation of the switches and for passive charge redistribution between the capacitors.

3. The circuit of claim 2 , wherein the at least one controller is also configured to transfer a fraction of the charge of all capacitors in accordance with a subset of the sample-and-hold elements as the analog combination signal to the converter core.

4. The circuit of claim 3 , wherein the at least one controller is configured to determine the subset in dependence on a selectable gain factor.

5. The circuit of claim 2 , wherein the capacitors of the sample-and-hold elements have different or identical capacitances.

6. The circuit of claim 2 , wherein the capacitors of the sample-and-hold elements are formed by a sampling capacitor of the quantizer.

7. A circuit comprising:
an input terminal configured to receive an analog input signal,
a combination element configured to combine a number of time-displaced signal values of the analog input signal to form an analog combination signal, and
a quantizer configured to convert the analog combination signal according to the successive approximation register method, wherein the quantizer comprises:
a converter core configured to receive the analog combination signal via passive charge redistribution from the combination element and to convert it into a digital output signal, and
a parallel connection of a number of digital-to-analog converter (DAC) capacitors as an input stage to a comparator forming the converter core.

8. The circuit of claim 7 ,
wherein the combination element comprises a number of sample-and-hold elements configured to sample and to hold the time-displaced signal values of the analog input signal at different times, and
wherein the capacitors of the sample-and-hold elements are formed by the DAC capacitors.

9. The circuit of claim 8 , wherein the switches of the sample-and-hold elements are arranged in a signal path from the input terminal to the converter core and between adjacent capacitors.

10. The circuit of claim 8 , wherein the switches of the sample-and-hold elements connect the respective capacitor optionally to ground, a reference potential and a floating potential.

11. The circuit of claim 1 , further comprising at least one controller configured to activate the combination element in such a manner that the time-displaced signal values are arranged at random times.

12. The circuit of claim 1 , further comprising at least one controller configured to activate the combination element in such a manner that the time-displaced signal values are arranged at times which have a distance from one another which is shorter than a conversion period of the quantizer for converting the analog combination signal into the digital output signal.

13. The circuit of claim 1 , further comprising at least one controller configured to activate the combination element in such a manner that a period between a time corresponding to a first signal value and a time corresponding to a last signal value is shorter than a conversion period of the quantizer for converting the analog combination signal into the digital output signal.

14. The circuit of claim 2 , wherein the at least one controller is configured to activate the combination element in such a manner that the capacitors of the sample-and-hold elements are charged in at least partially overlapping periods based on the analog input signal.

15. The circuit of claim 1 , further comprising:
a further input terminal configured to receive a further analog input signal,
a further combination element configured to combine a number of time-displaced signal values of the further analog input signal to form a further analog combination signal, and
a multiplexer configured to transfer optionally the analog combination signal or the further analog combination signal to the converter core of the quantizer.

16. The circuit of claim 15 , further comprising at least one controller configured to activate the combination element and the further combination element in such a manner that the time-displaced signal values of the analog input signal and the time-displaced signal values of the further analog input signal are interleaved in time.

17. The circuit of claim 15 ,
wherein the multiplexer is configured to transfer the analog combination signal and the further analog combination signal in each case in a number of iterations to the converter core of the quantizer, and
wherein the transferring of the analog combination signal and the transferring of the further analog combination signal is interleaved in time over a number of iterations.

18. The circuit of claim 1 , wherein the sample-and-hold elements branch from the path from the input terminal to the quantizer.

19. The circuit of claim 1 , wherein the quantizer is configured to convert the analog combination signal in accordance with the sigma-delta method.

20. A method comprising:
receiving an analog input signal,
sampling and holding a number of time-displaced signal values of the analog input signal at different times,
combining the time-displaced signal values of the analog input signal to obtain an analog combination signal,
transferring the analog combination signal via passive charge redistribution, and
converting the analog combination signal into a digital output signal.

21. The circuit of claim 7 , further comprising at least one controller configured to activate the combination element in such a manner that the time-displaced signal values are arranged at random times.

22. The circuit of claim 7 , further comprising at least one controller configured to activate the combination element in such a manner that a period between a time corresponding to a first signal value and a time corresponding to a last signal value is shorter than a conversion period of the quantizer for converting the analog combination signal into the digital output signal.

Assignees

• Infineon Technologies Ag

Inventors

• Pernull Martin
• Bogner Peter

Classifications

• H03M3/368 Primary

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/422

  having one quantiser only · CPC title

• G11C27/024

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• H03M1/0626

  by filtering · CPC title